nESL System Level Debug
The Novas nESL™ System-Level Debug Module extends the Verdi™ Automated Debug System for use at higher levels of abstraction - bridging the RTL, system, and software domains with a unified approach to debug that supports the critical elements of today's Electronic System Level (ESL) design methodologies.
nESL provides advanced debug capability in three areas common to most ESL environments:
- Transaction-level modeling and analysis
- SystemC design and verification
- Hardware/software co-design and co-verification
nESL benefits include:
- Increases understanding of SystemC model behavior for hardware designers
- Enables debug of code running on embedded processors for software designers
- Eases comprehension, analysis, and debug of complex protocols and buses
- Interoperates seamlessly with all popular design and verification languages and tools
nESL accelerates system-level debug
with advanced embedded platform technologies including
transaction analysis, SystemC tracing, and hardware/software
co-debug.
Transactions for Debug at Higher Levels of Abstraction
Abstraction is an important technique in the verification, analysis, and debug of complex systems because it hides confusing, low-level details so engineers can focus on vital information about the operation of the system under test. Transactions provide abstraction by representing the communication between system or design components using high-level operations rather than signal value changes. Using nESL's transaction-level debug and analysis features, you can explore and understand system operation at this same level of abstraction - without having to infer it from the signal-level details.
nESL provides unique, advanced transaction
capabilities. A dynamic spreadsheet and associated tools enable
analysis functions including bus loading, correlation across
bus bridges, and performance evaluation.
Transaction-level debug and analysis features include:
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Visualization and statistical analysis in waveforms, spreadsheets, graphs, and charts
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Specification and display of common and user-defined transaction relationships, such as parent/child or master/slave, in the waveform view
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Traversal of protocol stacks and hierarchies down to the signal-level details
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Support for complex transaction scenarios such as split or overlapping transactions
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Transaction extraction from the Novas Fast Signal Database (FSDB)
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- Automatic extraction for the following standard protocols using a library based on Spiratech® transaction technology: AMBA_AHB; AMBA_AHB_lite; AMBA_APB; AMBA_AXI; MPEG2_TS; OCP_IP; PCIe; UART; USB 2.0
- User-definable extraction based on SystemVerilog Assertion (SVA) description
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Support for transactions dumped to the FSDB from a variety of sources
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- Native (direct) dumping from SystemC, SystemVerilog, Vera, e
- Dumping from verification IP (Denali®, Spiratech®, other vendors)
- User coding with an available C API
This comprehensive feature set fully supports common transaction-level applications and activities, such as system-level performance and architecture optimization and protocol debug and analysis. For users that only require transaction capabilities, these features are also available in the nTX™ Transaction Module.
SystemC Source Code Debug
SystemC is the most common system-level design language in use today. nESL provides full support for models and systems described in SystemC with a mixture of general, hardware-oriented, and software-oriented debug features.
General features include:
- Compilation and importation of SystemC and mixed SystemC/HDL descriptions
- Automated signal and variable data dumping from the Open SystemC Initiative (OSCI) Reference Simulator
- Signal and variable data dumping from popular commercial simulators
- SystemC Verification (SCV) transaction data capture from the OSCI Reference Simulator and popular commercial simulators
- Annotation of signal data on source code descriptions
- Display and analysis of SystemC variables and transactions in waveform and spreadsheet views
Hardware-oriented features include:
The hardware-oriented features hide class library details and enable design exploration similar to an HDL model.
- Viewing and traversing instance hierarchy
- Tracing signal drivers and loads throughout hierarchy and across language boundaries
- Generating and viewing block diagrams rendered from the source code description
Software-oriented features include:
The software-oriented features support debug using methods traditionally employed for C/C++ descriptions.
- Tracing software stacks and abstract data structures
- Browsing class structure and details independent of instance hierarchy
- Interactive mode link to standard software debuggers like gdb
Hardware/Software Co-Debug
Developers of embedded software - device drivers and the like - often need to observe the interaction of their code running on the hardware platform to debug problems and ensure correct operation. A tight link between the software debugger and the associated hardware environment is thus required to allow programs running on embedded processors to be debugged in the context of the hardware.
Hardware/Software features include:
- A generalized interface for linking Verdi to commercial or proprietary software debuggers
- Time synchronization for correlation of software instructions, bus transactions, and signal activity
Summary
As designs become larger and more complex, the use of ESL-based design methodologies is increasing. To address this trend, the Novas nESL System-Level Debug module extends the Verdi Automated Debug System in support of the common elements of today's ESL environments- transaction-level modeling and analysis, SystemC design and verification, and hardware/software co-design and co-verification.
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