Transaction Level Modeling and Debug of SoCs
System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges. Transaction-Level Models (TLM) described at the top levels of design, and/or extracted from the design implementation promises to not only speedup verification but also ease design understanding, evaluation and analysis thus alleviating the design burdens at the SoC level.
We present here our research and development efforts in the development of multi-level adaptors and transformers, as well as analysis, visualization, and debug facilities that revolve around TLM and the opportunities it affords for cooperative development among architect and design teams.
INTRODUCTION
Feature-rich consumer electronics are becoming increasingly common. The shrinking design features of nanometer design processes have empowered the development of designs with many millions of gates. The trade-off, however, has been an exponential escalation of system design complexity. To make matters worse, the large design size coupled with strict performance constraints, have given rise to physical-based synthesis and verification flows where the RTL design is a key fulcrum for design analysis, optimization, and validation.
System-level architects work with application developers to develop the application target and the design functional requirement; then comes, from top to bottom, high level modelling and test plan specification followed by design implementation and integration at the Register Transfer Level (RTL) and realization at the physical level.
RTL is the workhorse of design implementation because tools for design analysis, estimation, and backend realization such as synthesis from RTL to gates are quite mature. However, with RTL abstraction at the centre of design and verification activities, using varied characterization metrics such as performance and power consumption, a serious lag in engineer productivity arises. Too frequently, RTL is the pivot point for trade-off analysis, verification and debug, resulting in long and seemingly endless design iterations. This leads to the so-called design and verification productivity gap and is responsible for the recent swell in long development schedules for SoC designs and missed market opportunities for their applications.
It has also become quite evident that analysis at the RT level does not scale with the increased complexity of the design. The tremendous level of detail in RTL means exceedingly slow validation and extremely large trace data making it almost impossible to perform effective analysis and evaluation of the system design. Large size and compound complexity also necessarily means more corner cases, more latent bugs, and a dip in design quality. A new layer of abstraction on top of RTL where the system functionality and the design implementation (including estimates from the physical world) come together for trade-off analysis, verification and debug is required.
In order to address rising design complexity and the challenge of managing the increased detail and ensuing verification slowdown, there has been a rising interest in modelling, analyzing, and verifying system-level function and target architecture options at the level of system transactions. Transaction- Level Modelling (TLM) has recently been widely recognized as a useful paradigm for improving modelling efficiency, and verification performance [4]. TLM is the best current practical incarnation of the long sought articulation point for system design and verification; the place at which design specification and implementation, and the design team - architects and designers -- can come together to make educated design choices as well as diagnose and correct errors [5]. This level, if connected to RTL [1], has been shown to give a tremendous boon for reducing RTL-based design iterations and validation runtimes. TLM can alleviate the burdens of the productivity gap as it is adopted into the methodology, and as EDA tools that make use of this abstraction become commonly available. We describe here our research and development efforts that leverage the TL abstraction for modelling, analysis and debug. <click here to download complete paper>