Design and Debug with Advanced Languages:
Challenges & Opportunities for SystemVerilog
Faced with increasing design complexity, growing IC capacity, mounting cost, escalating risk, stagnant-maybe even declining-engineering productivity, and shrinking timeto- market, our industry as a whole is rallying around advanced design, verification and debug languages. These languages build on the experiences and lessons of the past, integrate recent successes, and open the door to innovative design, verification, and debug practices. SystemVerilog is one such example of a language that builds on Verilog-2001, folds formerly proprietary test generation facilities found only in testbench languages such as Vera and Temporal e [12], and makes a leap forward by also including response-monitoring capabilities of assertions from temporal OVA and PSL. PSL itself comes primarily from Sugar but also combines numerous concepts and input from the developers of ForSpec [3], Temporal e, and CBV [7]. The potential of SystemVerilog is not merely in its impressive host of useful elements, but also lies in the benefits of a unifying coherent framework for a comprehensive design, verification, and debug methodology. The language adds design abstraction, data encapsulation, flexibility and reuse, revamped syntax and semantics, and numerous facilities for productivity enhancements. We overview here several key elements of SystemVerilog focusing on their design and debug aspects; the challenges and the opportunities they pose.
Introduction
Advanced languages promise to usher in a new era in designer productivity, and increased product quality. Many design and debug prospects lay ahead: Remedies to many current woes but with future challenges and opportunities as well. Design is a creative yet methodical process; giving the engineer more constructs and concepts to work with can give a tremendous yield [17]. In this paper, we use SystemVerilog as a representative of such advanced languages that has benefited from a large legacy (thousands of Verilog and VHDL designs and years of industry support by numerous vendors), a lengthy user experience with documented "wish-lists", and an infusion of-relatively recent yet appealing-object-oriented verification constructs. For example, abstract modeling and enhanced data types in SystemVerilog [1] open the door to system-level behavioral design, and therefore permit HDLbased design to move from the RTL implementation realm to the algorithmic one. The data aggregation constructs (such as struct and the like) make debugging much more effective. It should be noted that the increased abstraction translates into higher productivity, as we will see, yet has minimal or no adverse affect on synthesis efficiency [13]. Debugging also requires sound and rigorous design knowledge analysis, management, and manipulation. Enhanced modeling, such as transaction-level, not only allows for increased debug tool scalability with the design size because of data grouping and organization, it makes inroads in terms of design understanding as well, with the more abstract representation and visualization. SystemVerilog also adds a multitude of constructs in process blocks that make intent inference precise; this bodes well for all the design tools, particularly debuggers tasked with relieving the mental burden of designers through automation [8]. Debuggers must also present the design data, whether original or derived, in a personable yet efficient fashion; presentation is as much a part of a tool that involves the human element as any of its other algorithmic respects. A multitude of abstractions makes data organization, exploration, and presentation much more tenable to the debug user. Separating behavior from communication is another prominent philosophy in SystemVerilog that permits tremendous gains in terms of design reuse within the current implementation, across different versions that serve different markets with varied trade-offs, and across future generations of the same design. We discuss these core design enhancement facilities and their debug counterpart in the Section titled "Enhanced Design and Debug".
Object-orientation of SystemVerilog adds flexibility and reuse. Objects allow easy testbench creation and maintenance in design; however, they pose a new challenge to traditionally hardware-centric debug. Debuggers must be enhanced with fresh approaches that pull in concepts from the software domain such as class hierarchies, and object sequence diagrams to track both the static and dynamic nature of the design [4]. Modeling and synchronization features such as threads, semaphores, and mailboxes enhance testbench creation and description. These pose, however, a unique challenge to current-day source-driven hardware debuggers that must now not only account for all the different threads (ids and timestamps) involved, but must also develop innovative analysis and visualization techniques to address this additional level of concurrency. The increased design productivity must be countered equally on the debug side; otherwise the productivity bottleneck would only move from the design creation stage to the analysis and debug stage in the system development process. Testbench facilities and their debug is described in the Section titled "Enhanced Testbench".
SystemVerilog assertions bring forth compositional and constrained design, synthesis, and verification. Assertions improve IP-based design, and their utility is high for educated debug. Assertions can be used to not only drive the debugging process to localize the error symptom but can also help to diagnose the cause of the faulty design behavior [19]. Assertions and their benefits to design and debug is overviewed in the Section titled "Assertion-Based Design and Debug".
In this paper, we shed light on these issues, and share our views on where design and debug can be in the near future, using examples and figures, where appropriate, for illustration. <click here to download complete paper>