Novas Debug Technology
The overarching driver of chip design is the relentless march of "Moore's Law." The real issue is not the particular period of time in which the content of a chip doubles, but rather the fact that complexity increases exponentially faster than size. Packing more functions and faster operations into larger chips built with smaller geometries undoubtedly makes them extremely complex and hence very difficult to understand, debug, and analyze.
As chip size and complexity increases, design verification becomes an increasingly costly and time-consuming part of product development. Products such as simulators, formal verification tools, and hardware emulators and accelerators automate the process of detecting design defects, and have accelerated the rate at which these "bugs" can be found. However, the debug part of the process has remained a bottleneck, because it requires an engineer with knowledge of the design to spend time trying to figure out how the design is supposed to work and understand why it doesn't function as intended.
New languages as well as new methodologies have emerged to tackle the complexity problem, including:
- Hardware verification languages (HVLs) and testbench automation tools, which help manage complexity by providing higher-level abstractions for creating block and chip-level functional tests;
- Property and assertion languages, which help increase coverage by providing highly efficient and reusable formal ways to specify intended behavior;
- New simulators that increase verification coverage through support of assertion languages and dynamic assertion checking; and
- Formal and semi-formal verification that augment simulation through the application of rigorous mathematical analysis.
These techniques while helping with the verification complexity actually compound the debug and analysis problem. Sophisticated tools to understand, debug, and analyze designs are now a necessity, rather than a nice-to-have luxury. Without such tools, the risk for missing schedules is high. Statistics on system-on-chip (SoC) design costs published by the International Technology Roadmap for Semiconductors (ITRS) project that one million dollars is added to the design budget for every month a project schedule slips, in addition to the opportunity cost of revenue lost by entering the market late. Subsequently, the ability of designers to comprehend complex and unfamiliar logic is critical, and the tools enabling them to do so must reach new levels. This requires fundamental advances in debug automation.
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