Transaction-Based Debug of PCI Express Embedded SoC Platforms
Semiconductor advances have enabled designers to take advantage of the increased silicon real estate to put entire systems on a single chip. Such system-on-chip (SoC) designs are made up of several complex functional units (blocks) built around a standard or custom bus with a well-defined protocol. Functional verification of large SoC designs presents new and interesting challenges to chip development teams. In particular, simulating at the register transfer level (RTL) now generates tremendous amounts of signal-level data that must be tracked and analyzed, greatly increasing the complexity of the verification and debug process. Design and verification engineers can realize significant productivity gains by viewing and analyzing this data at a higher level of abstraction.
The functional units of SoCs often communicate through numerous buses which are based on standard or custom protocols such as PCI Express, a highly optimized serial protocol. While analyzing the communication across existing parallel bus architectures is complex, serial protocols pose an even greater challenge for verification and debug. Serial protocols encode the control and data signals into a stream of bits that are then transported across a much narrower interconnect. In the case of modern interface protocols like PCI Express, the data is placed into packets, scrambled for EMI reduction, encoded (8b/10b) for DC balancing, and then finally serialized for transmission across the wires.
In addition, many serial interface protocols utilize split transactions. Again using PCI Express as an example, commands are split into multiple parts and then pipelined to improve the performance and efficiency of the bus. This is achieved by separating the request and the request acknowledgement phase of the transaction, enabling the processing of commands before previous commands are completed. For example, one requester might issue a read command, and while waiting on the response to the read, the requester may issue other reads and writes, thus increasing the efficiency of the system. It is obvious that analyzing this data, which has been serialized, encoded, and packetized, is impractical at the pin-level with standard debug tools.