Assertion-Based Hardware Debugging - presented at DVCon
Today's increasing design complexity requires innovation in both debug automation, and user interaction. We present here a novel query-based method that uses assertions as queries to assist in the domain of hardware debugging. Our approach is generally applicable to hardware debug, and is independent of the particulars of the input design or the assertion description language. We show how assertions drive the debugging process in order to diagnose the cause of the faulty behavior through the unique techniques of trace slicing, and trace dicing. We also present here a new visualization and user interaction technique specifically designed for complex systems with numerous component interactions and abundant control flows. The visualization approach leverages design and assertion spans to present the debugging information to the user in a refined detail of abstraction and permit adequate interaction. An experimental debugging system incorporating assertion-based debug guidance has been implemented. Experimental results for productivity enhancements from a case study will be presented.
Introduction
Debugging is one of the most challenging, yet least researched, area in hardware design. It has for the most part, besides notable exceptions [1], retained the flavor of software source-level debugging. Today's increasing design complexity, as evidenced by the prevalence of SoC designs, coupled with the ever decreasing time-to-market requires innovation in both debug automation, and user interaction. The former requires more behavior analysis power, and the latter more concise albeit expressive user guidance as well as hardware-domain-specific debugging environments.
In order to address these shortcomings, this paper presents a novel query-based method for hardware debugging. The original form of algorithmic debugging, introduced by Shapiro [2], was developed for software Logic Programming. The algorithmic debugger traversed the execution tree and interacted with the user by asking about the intended behavior of each procedure until a bug was located and corrected. In this work, we adapt that notion and use assertions as queries to assist in the domain of hardware debugging. Assertions can be embodied in the procedural program itself, or specified externally to it typically in a concise yet expressive declarative form. Our approach is generally applicable to hardware debug, and is independent of the particulars of the input design or the assertion specification. We show, here, how assertions drive the debugging process in order to diagnose the cause of the faulty behavior. The expressions of an assertion, and signal support therein, are used to isolate the relevant behavior error using the unique techniques of trace slicing, and trace dicing that we introduce. These methods were influenced strongly by program slicing of Weiser [3]. In addition, multiple assertions can be used as constraints to localize errors even further in a multi-assertion form of trace slicing and dicing. User guidance in this endeavor, while limited, is crucial for practicality of efficiency and computation considerations.
Over the past two decades, visualization has been shown to be key for adequate user interaction and an extremely effective tool for facilitating debug in general, and of concurrent systems in particular. To this end, we also present here a new visualization and user interaction technique specifically designed for complex systems with numerous component interactions and abundant control flows. The visualization approach leverages design and assertion spans to present the information to the user in a refined detail of abstraction therefore enabling an adequate level of interaction with the user (designer and/or verification engineer).
The next section presents the foundation of our work; a design behavior extraction, analysis, and exploration infrastructure. <click to download complete paper>