Visibility Enhancement for Silicon Debug - Presented at DAC 2006
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part. Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL). Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems.
The process for productizing and delivering an idea to market can typically be broken into two major stages: concept-to-prototype and prototype-to-volume. For IC designs, the first stage encompasses the time from creating the specification to the arrival of first silicon prototypes. The second stage involves testing and debug of these silicon prototypes using automated test equipment (ATE), performing in-situ system validation of the prototypes, and ensuring the manufacturing process is sufficient for volume production. Recent trends indicate that while the amount of time is stable to slightly decreasing for the first stage, the time required to move from prototype to volume production is increasing[1],[2]. We propose new technologies that, working with on-chip debug infrastructure, address the portion of these trends associated with silicon debug during in-situ system validation.
When errors are detected, the silicon prototypes must be debugged for functional errors or diagnosed for physical defects. Increasing device complexity means efficient silicon debug is an essential step of the product development process[3]. Figure 1 shows the current average amount of time required for these two stages.
Figure 1
Silicon debug is difficult primarily due to the lack of internal signal value visibility. Key factors which make silicon debug difficult include:
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Limited silicon signal data visibility prevents understanding of internal behavior
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Silicon errors may either be functional bugs or physical defects - creating unrepeatable errors
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Silicon debug data, such as signal values, is usually associated with a gate-level netlist and not the RTL with which the designer is familiar
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Current environments for silicon debug are different from the design and verification environment (file formats, tools, etc.)