Novas is committed to providing the industry with the latest information on advanced debug and verification technology for IC, SoC and FPGA design.
Please download the following white papers to learn more.
Visibility Enhancement for Simulation Methodology Backgrounder
Software simulation is the primary method used to verify logic in integrated circuit (IC) designs. When simulation discovers logic errors through unexpected logical behavior, users must trace the causes. This tracing requires that logic values be recorded during simulation. For large designs, recording these values adds enormous overhead to the simulation process. This causes users to adopt a variety of costly strategies for reducing this overhead. New Visibility Enhancement technology enables methodologies that reduce the need for this manual effort and improve the overall productivity of logic verification with simulation. This technology identifies a minimal subset of signals required for full visibility and automatically expands the data for other signals from this recorded subset during debug.
Visibility Enhancement Technology for Simulation
Although new tools, improved methodologies and higher levels of abstraction are shortening design and verification times, the time required to (and difficulty associated with) determining the root cause of problems found in large, long simulations is growing.
A key factor stretching debug times for full-chip verification applications is the impact of observing signal values. Effective debug requires the engineer to observe and record signal values over time so that the causes of design behavior can be investigated and understood. But observing signal values impacts design and verification. It takes time to dump and record the signal values that must be observed. As a result, simulation run-times stretch. For large chips, the sheer quantity of data limits what can be observed, leading to methodologies that require multiple simulation runs to isolate the cause of a given problem if "the right signals" aren't captured the first time around.
Visibility enhancement provides the engineer a way to optimize visibility by making tradeoffs between impact and observability. With lots of impact, it is easy to see everything. With no impact, nothing can be observed. The trick is to find a way to minimize impact while achieving full visibility - or at least enough visibility to debug the problem.
Visibility Enhancement for Silicon Debug - Presented at DAC 2006
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require the instrumentation of on-chip logic for extracting the internal register data from in situ silicon. Unfortunately, lack of visibility of the combinational network values impedes the ability to functionally debug the silicon part. Visibility enhancement techniques enable the virtual observation of combinational nodes with minimal computational overhead. These techniques also cover the register selection analysis for DFD and multi-level design abstraction correlation for viewing values at the register transfer level (RTL). Experimental results show that visibility enhancement techniques can leverage a small amount of extracted data to provide a high amount of computed combinational signal data. Visibility enhancement provides the needed connection between data obtained from the DFD logic and HDL simulation-related debug systems.
Practical Applications of Data Abstraction Techniques for Embedded Systems debug - presented at IPSoC
Current embedded processor-based platforms, while enabling the rapid implementation of complex and wide ranging functionality on a single device, present new challenges in terms of overall design methodology. One of the most significant is the debug of functional operation, the implementation of which is often spread across multiple software and hardware components, and masked in protocol layers and signal transformations.
This paper will present in detail practical applications that illustrate the host of issues that hamper the debug of an embedded platform as well as methods to mitigate these problems. We will discuss the debug of a "Network on Chip" (NoC) communication mechanism, which while providing potential performance, power and interconnect flexibility gains for the target system, disguises implementation detail to a great degree. We will additionally demonstrate the use of an FPGA-based rapid prototyping solution, which enhances verification performance gains by hiding or transforming circuit structure, but to the possible detriment of signal visibility.
Transaction-based Debug of PCI Express Embedded SoC Platforms - presented at IPSoC
Embedded system platforms typically contain at least one processing element such as a microprocessor or digital signal processor along with peripherals, random logic, and memory and interface modules. They also employ a bus-based protocol architecture. Bugs that interact both inside blocks and at the bus communication level can be particularly problematic during verification. Multi-bus protocols within the system on chip itself further increase the complexity of this problem. By analyzing bus behavior at the transaction level, design behavior can be much easier to understand and debug.
This requires an extensible architecture that enables transaction-level debugging and an open API approach to verification IP, which includes bus protocol checkers, bus transactors, and traffic generation mechanisms. In particular, the verification IP and debug environment must be able to recognize and record transactions (extraction), perform protocol verification as well as output rules and results, and also calculate bus statistics to ensure functional coverage and utilization. These built-in bus protocol checkers and analysis engines, along with new visualization and animation capabilities, must address the unique requirements of debugging complex serial interconnect standards such as PCI Express.
This paper will look at a typical application of transactions for embedded processor platform modeling and debug across a PCI Express based system. It will examine how transactions are leveraged to improve the performance, verification, and simulation efficiency of embedded designs, and illustrate specific debug issues and methodologies associated with them. < Read more>
Transaction-Level Modelling and Debug of SoCs - presented at IPSoC
System-on-Chip (SoC) designs are becoming increasingly complex. Modelling, verification, and debug facilities at RTL have become quite inadequate in the face of rising design challenges. Transaction-Level Models (TLM) described at the top levels of design, and/or extracted from the design implementation promises to not only speed-up verification but also ease design understanding, evaluation and analysis thus alleviating the design burdens at the SoC level.
We present here our research and development efforts in the development of multi-level adaptors and transformers, as well as analysis, visualization, and debug facilities that revolve around TLM and the opportunities it affords for cooperative development among architect and design teams. < Read more >
Design and Debug with Advanced Languages: Challenges and Opportunities for SystemVerilog- presented at DVCon
Faced with increasing design complexity, growing IC capacity, mounting cost, escalating risk, stagnant-maybe even declining-engineering productivity, and shrinking time-to-market, our industry as a whole is rallying around advanced design, verification and debug languages. These languages build on the experiences and lessons of the past, integrate recent successes, and open the door to innovative design, verification, and debug practices. SystemVerilog is one such example of a language that builds on Verilog-2001, folds formerly proprietary test generation facilities found only in testbench languages such as Vera and Temporal e [12], and makes a leap forward by also including response-monitoring capabilities of assertions from temporal OVA and PSL. PSL itself comes primarily from Sugar but also combines numerous concepts and input from the developers of ForSpec [3], Temporal e, and CBV [7]. The potential of SystemVerilog is not merely in its impressive host of useful elements, but also lies in the benefits of a unifying coherent framework for a comprehensive design, verification, and debug methodology. The language adds design abstraction, data encapsulation, flexibility and reuse, revamped syntax and semantics, and numerous facilities for productivity enhancements. We overview here several key elements of SystemVerilog focusing on their design and debug aspects; the challenges and the opportunities they pose. < Read more >
Assertion-Based Hardware Debugging - presented at DVCon
Today's increasing design complexity requires innovation in both debug automation, and user interaction. We present here a novel query-based method that uses assertions as queries to assist in the domain of hardware debugging. Our approach is generally applicable to hardware debug, and is independent of the particulars of the input design or the assertion description language. We show how assertions drive the debugging process in order to diagnose the cause of the faulty behavior through the unique techniques of trace slicing, and trace dicing. We also present here a new visualization and user interaction technique specifically designed for complex systems with numerous component interactions and abundant control flows. The visualization approach leverages design and assertion spans to present the debugging information to the user in a refined detail of abstraction and permit adequate interaction. An experimental debugging system incorporating assertion-based debug guidance has been implemented. Experimental results for productivity enhancements from a case study will be presented. < Read more >
Novas Debug Technology White Paper
As chip size and complexity increases, design verification becomes an increasingly costly and time-consuming part of product development. Products such as simulators, formal verification tools, and hardware emulators and accelerators automate the process of detecting design defects, and have accelerated the rate at which these "bugs" can be found. However, the debug part of the process has remained a bottleneck, because it requires an engineer with knowledge of the design to spend time trying to figure out how the design is supposed to work and understand why it doesn't function as intended.
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Advanced Techniques for RTL Debugging - Presented at DAC
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) source. This process is helpful in locating errors but does little to help designers reason about the how and why. Designers usually have to build a mental image of how data is propagated and used over the simulation run. As designs get more and more complex, there is a need to facilitate this reasoning process, and automate the debugging. In this paper, we present innovative debug techniques to address this shortage in adequate facilities for reasoning about behavior, and debugging errors. Our approach delivers significant technology advances in RTL debugging; it is the first comprehensive and methodical approach of its kind that extracts, analyzes, traces, explores, and queries a design's multi-cycle temporal behavior. We show how our automatic tracing scheme can shorten debugging time by orders of magnitude for unfamiliar designs. We also demonstrate how the advanced debug techniques reduce the number of regression iterations. <Read more>