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Novas Design Comprehension Solutions
Novas orchestrates a collection of leading-edge solutions that ease design comprehension throughout the verification flow, from systems to silicon. Our debug systems reduce the time it takes to understand complex logic, giving you more time to spend on adding value to your design. Our new visibility enhancement products optimize verification resources by reducing the amount of data required to gain full visibility into design behavior, cutting simulation and emulation run times, reducing disk space requirements, and enabling effective silicon debug.
Novas design comprehension solutions include:
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Debug Automation to accelerate tracing of causes and effects
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Visibility Enhancement to reduce the cost of verification
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Methodology Unification to simplify the flow through design, verification, and analysis
Greater Overall Design Productivity
Debug - observing, tracing, visualizing, and understanding design behavior - is a necessary part of the design and verification process. Recording the data required to comprehend complex designs consumes a significant amount of the verification resources on a typical project. Methodologies for recording that data are inconsistent and the time required unpredictable.
Verification consumes up to 70% of design effort and debug takes up to 50% of that time - this means up to 35% of your overall design time is spent understanding how a design works or why it doesn't. Recording the data necessary for debug consumes additional verification resources by slowing simulation and emulation and by forcing designers to spend time figuring out what to record because recording everything takes too long and too much space
Novas solutions cut the time it takes to comprehend your design from systems to silicon by half or more, enabling you to:
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Achieve tight schedules
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Cut verification costs
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Spend more time adding value
Automated Debug in the Design and Verification Flow
Debug is necessary at every stage of the design and verification methodology. Novas' solutions address the unique requirements of each stage of the flow and provide a complete unified debugging environment from systems to silicon to help you debug more efficiently:
RTL & Gate-level Debug
Verdi™ Automated Debug System - A full-featured debug system with innovative behavior analysis technology that eliminates much manual debug effort. Verdi technology:
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Automatically traces causal logic over many cycles
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Extracts, isolates, and displays pertinent logic in temporal flow views that combine both time and structure for rapid comprehension of complex sequential logic
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Provides a unified debug environment that supports the widest range of standard design languages and popular verification tools
Assertion and Testbench Debug
The Verdi system provides:
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Seamless debug of design, testbench, and assertions in a single environment
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Support for standard testbench and assertion languages and popular verification tools
Transaction Analysis
The Novas nTX™ Transaction module extends the Verdi™ Automated Debug System with advanced capabilities to extract, view, and analyze transactions. nTX's transaction capabilities simplify the process of understanding complex SoC operations by enabling debug and analysis at a higher level of abstraction.
The nTX module provide
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Eases comprehension of complex protocols and buses
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Provides fast and flexible integration with a wide variety of verification environments
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Minimizes ramp up time for designs utilizing standard protocols
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Leverages standard SystemVerilog Assertion (SVA) syntax to describe and extract transactions for non-standard protocols
Design Implementation Analysis
nAnalyzer™ Design Implementation Analysis - Analysis module that extends our Verdi solution to provide a single environment for evaluating and debugging critical timing, signal integrity and power issues. nAnalyzer technology:
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Extracts and analyzes clocks, clock trees, clock domains, reset trees, and other implementation-level details
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Imports and processes delay and signal activity information to reveal potential timing and power problems
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Interfaces with popular timing and power analysis tools for rapid understanding of analysis results
Visibility Enhancement
The Siloti™ family of Visibility Enhancement (VE) products transforms verification methodologies by eliminating the overhead associated with dumping data for all the signals in a design. Siloti technology provides full visibility of internal signals for complex IC and system-on-chip (SoC) designs by identifying the minimal set of signals for dumping, generating "on-demand" the rest of the signal data, and correlating gate-level results to the register transfer level (RTL) source code. Siloti products are used during full-chip simulation, emulation and first-silicon prototyping to:
- Achieve full visibility into the functional operation of designs with limited impact on verification performance;
- Enable the analysis and debug of gate-level verification results on the RTL design; and thus
- Reduce overall verification time and cost.
Full-Chip Simulation Visibility Enhancement
Siloti SimVE visibility enhancement solution - Allows you to optimize your simulation methodology. Today you probably run regression simulation without recording any signal values. This means you must run at least one more simulation before you can debug, and you must either record everything (very costly) or guess at which signals you need (error prone - leads to a third run.) The Siloti solution enable full-chip functional debug after every regression simulation run, with minimal impact on simulator performance. Or, continue to run your regression with no recording, but immediately turn on recording of all the essential signals on the second run. This makes your time-to-debug predictable and eliminates guesswork and wasted resources.
Siloti SimVE technology provides:
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The ability to immediately start debugging after discovering an error
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High visibility with minimal impact
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4X faster simulation compared to recording all signal value changes
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25% performance impact compared to recording no value changes
Emulation and Prototyping, Silicon Visibility Enhancement
The Siloti product works with emulators, prototypes, and Design for Debug (DFD)-enabled chips to provide high visibility with low impact. Recording signal values in emulation and prototypes requires costly instrumentation that increases the FPGA image size, reduces capacity, and slows emulation to a crawl. Observing signal values from actual chips installed in boards requires special logic and is inherently limited.
Siloti technology provides engineers the ability to:
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Reduce the overhead required for recording values from emulation and prototypes
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Dramatically improve visibility with limited data from design-for-debug enabled chips
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Eliminate guesswork determining which signals to record
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Reduce emulation debug by a factor of four
Complementary Products
Novas provides tightly-integrated add-on products that go beyond debug and work with the Verdi system to improve productivity throughout the design and verification process:
nECO- Automated gate-level netlist modification tool that propagates changes throughout the design hierarchy and automatically creates new nets and ports as required.
nAnalyzer™ - Design Implementation Analysis solution that provides a single environment for understanding and debugging critical design implementation issues that typically arise during synthesis and related activities that transform an RTL description into a gate-level netlist that is ready for tapeout.
Additional Modules
Looking for Debussy®? Click here for more information about our basic but powerful modular debug solution.