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SILOTI VISIBILITY ENHANCEMENT PRODUCTS
The Siloti™ family of Visibility Enhancement (VE) products transforms verification methodologies by eliminating the overhead associated with dumping data for all the signals in a design. Siloti technology provides full visibility of internal signals for complex IC and system-on-chip (SoC) designs by identifying the minimal set of signals for dumping, generating "on-demand" the rest of the signal data, and correlating gate-level results to the register transfer level (RTL) source code. Siloti products are used during full-chip simulation, emulation and first-silicon prototyping to:
- Achieve full visibility into the functional operation of designs with limited impact on verification performance;
- Enable the analysis and debug of gate-level verification results on the RTL design; and thus
- Reduce overall verification time and cost.
Improve Verification Productivity and Predictability
Powerful, breakthrough visibility enhancement technologies accelerate the process of understanding and repairing the sources of erroneous behavior by:
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Deriving a minimum set of "essential" signals that should be captured during verification;
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Analyzing the limited set of captured signal data and automatically regenerating missing information; and
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Correlating signal data associated with low-level chip representations to RTL descriptions.
Inadequate Visibility Hampers Verification
Observing enough signals to isolate and analyze the root cause of problems found during the verification of large designs is increasingly difficult, expensive, and time-consuming due to:
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The massive amounts of data produced;
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Detrimental effects of observing signal data on the performance of verification tools;
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Limitations on the amount and type of signal data accessible using some hardware-based verification approaches; and
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Difficulties in interpreting signal data that matches unfamiliar low-level design representations.
Visibility Enhancement Technologies
Siloti VE technology combines visibility analysis capabilities with a data expansion engine to optimize verification and reduce the impact of observation on performance and critical design and verification resources.
Visibility Analysis Engine
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Analyzes RTL and netlist representations to determine minimum set of essential signals required for full visibility when used with Siloti data expansion
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Provides flexibility needed to target entire design or only those blocks and signals of interest
Data Expansion Engine
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Automatically computes missing signal data based on essential signal data and design knowledge provided by RTL or netlist
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Optimizes data regeneration process by computing "on-demand" only those values required by the user-driven debug process
In addition to these core capabilities, the optional Siloti Abstraction Correlation and Replay modules make visibility and verification of gate-level verification results more efficient.
Abstraction Correlation Module
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Automatically maps gate-level verification results to RTL design descriptions
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Interoperates seamlessly with the data expansion engine to enable analysis and debug with full visibility on the RTL design
Replay Module
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Operates on captured essential signal data
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Enables incremental, timing-accurate simulations for specified time windows, eliminating the need to re-run full timing simulation when an error is detected
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Provides full visibility for all signals in specified time windows, enabling quick analysis and debug of timing errors
Optimize Verification and Validation Methodologies
Novas' Siloti visibility enhancement capabilities dramatically improve full-chip simulation, emulation, first-silicon prototype and silicon validation methodologies when errors are discovered. It speeds comprehension of design operation and enables better utilization of verification resources by:
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Minimizing the set of signals dumped during simulation, improving run time performance and reducing dump file size while retaining full visibility;
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Eliminating multiple simulation iterations typically required to isolate and fix problems;
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Reducing the data that must be captured during slow, timing-accurate gate-level simulations;
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Minimizing the set of signals probed during emulation or prototype operation, thus improving verification performance while retaining full visibility; and
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Correlating gate-level verification results back to RTL source for easy understanding and debug of design behavior.
Accelerate Debug and Analysis
Siloti tool users can leverage the benefits of full visibility by bringing signal data into Novas' market-leading Verdi™ Automated Debug System for enhanced gate or RTL debug. The Siloti capabilities automatically correlates and expands data during debug, so that engineers can take advantage of the powerful visualization and automation capabilities in the Verdi system to:
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Extract, isolate and display relevant logic in flexible and powerful design views;
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Automate behavior tracing with unique behavior analysis technology; and
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Reveal the operation and interaction between the design, assertions and test bench.
The Siloti Visibility Enhancement environment provides the Verdi Automated Debug System with requested signal value data "on-demand", optimizing performance and compute memory resources.
The Siloti Visibility Enhancement products solve the costly problem of decreased signal visibility during full-chip simulation, emulation, first silicon prototyping and system validation. You can immediately realize the benefits of greater design comprehension, more predictable verification and validation cycles, and faster debug of complex ICs and SoCs.
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