Novas Software: nECO

Designers of complex chips find many reasons to modify the netlist. Often these changes come late in the design process where errors are very costly. Netlist changes are error-prone because the netlist is large, complex, unfamiliar, and hard to understand. Errors such as changing the wrong gate or making a typo are far too common.

nECO improves users' ability to make accurate netlist changes by making it easy to understand the necessary change in context. To change a design with nECO, users first isolate the relevant logic using Verdi's and Debussy's standard views and analysis techniques. They then use a special schematic window in nECO modify the design.

Users control how nECO writes the modified design out to a new source code netlist. They can choose to write out the changed files, all logic in the specified hierarchical scope and below, or the entire design. nECO generates a report that details the changes and maintains the original file structure, including white space, so that the old and new files can be easily compared.. Comments are automatically placed in the new netlist source files identifying where changes were made.

nECO provides special features for managing spare cells. A list of spare cells can be derived from the design via a special naming convention, read from a file, or written to a file.

With Novas' debug systems and nECO, netlist changes are no longer tedious and error-prone. By locating the logic and isolating it, users understand exactly what they are changing so verification time and effort are reduced.

• Extends Verdi and Debussy to support netlist-level ECOs.
• Isolates the logic that needs to change.
• Changes the design in the context of the familiar Novas debug environment.
• Writes a modified design to Verilog netlist with comments.
• Generates reports to track and manage changes in the context of the source code control process.