Blue Pearl Software's Timing Constraint Generator identifies false and multi-cycle paths in complex digital chip designs known as timing exceptions. The tight integration with Novas' Verdi Automated Debug System allows these generated paths to be viewed schematically or in the source code for analysis and verification. Assertions generated by Blue Pearl are used by Verdi to assist in understanding of the timing exceptions and to enhance the verification suite. Generated testbenches are available in Verdi's powerful fsdb format for waveform analysis.