Aldec provides HDL simulation technology with an industry proven support for VHDL, Verilog, SystemVerilog, assertion languages (OVA, PSL, and SVA) and SystemC. Aldec's simulators (Riviera and Active-HDL) can store signal history during simulation in a fast signal database (FSDB). The FSDB file is then used by the Verdi Automated Debug System or Debussy Debug System to display waveforms and annotate signal values in other debugging tools. Aldec supports the latest additions to the FSDB format such as storing information about assertions. Aldec's simulator can also be controlled directly from the Verdi GUI. This allows interactive simulation, stepping through the source code and forcing signal values in the simulated model.