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See an in-depth demo

(click here for more details)

What we’ll be showing

• Essential Signal Analysis (ESA) to identify the critical subset of signals that must be recorded during simulation
• On-the-fly Data Expansion (DE) to enable full visibility during debug (Verdi)
• Replay for timing-accurate regeneration of signal data based on the Essential Signal (ES) data set

What’s new for 2008

• Enhanced ease-of-use:  Get the benefits of Siloti with little or no impact on existing Verdi debug flow
• Replay:  Get the benefits of Siloti – faster simulations and smaller FSDB files – with gate-level timing simulations

What we’ll be showing

• Automatically tracing design activity using Behavior Analysis (BA) technology and Verdi’s patented Temporal Flow View (TFV)
• Checking SystemVerilog Assertions (SVA) post-simulation using Verdi’s Assertion Evaluator
• Automatically tracing the root cause of an SVA failure using Verdi’s Assertion Analyzer
• Logging SystemVerilog Testbench (SVTB) details to FSDB for post-simulation analysis in waveforms and specialized tabular views
• Navigating and viewing SVTB code using the new declaration-based Testbench Browser
• Tracking and debugging SVTB code in interactive mode using call-stack and variable details annotated on the Testbench Browser

What’s new for 2008

• Logging SystemVerilog Testbench (SVTB) details to FSDB for post-simulation analysis in waveforms and specialized tabular views
• Navigating and viewing SVTB code using the new declaration-based Testbench Browser
• Tracking and debugging SVTB code in interactive mode using call-stack and variable details annotated on the Testbench Browser

Verification planning is an essential part of the chip design process, yet experience shows that it is seldom attempted with any rigor.  Enthusiasm for the task tails off rapidly as soon as the “real work” of coding the testbench becomes feasible.  Limited knowledge of how to do effective verification planning, low personal motivation and benefits, and lack of permission are common reasons for abandoning the planning early.  Subsequent verification tends to be inefficient, impacting both the quality of the design and delivery schedule, and leading to a stressful and unsatisfying project experience for all involved.

In this one hour presentation, Dr. David Robinson from Verilab provides an introduction to Requirements Based Verification, a verification planning approach which aims for efficiency by allowing project stakeholders visibility into the size, scope, progress and risk of the overall verification process.  Good risk-based visibility at all stages helps ensure that verification proceeds with few surprises.

This presentation is extracted from Verilab's Requirements Based Verification review process, and covers the following topics:

·         Requirements Based Verification overview

·         How to create good requirements

·         Risk based prioritization

The presentation will be of interest to verification engineers and managers who would like to improve the efficiency of their verification efforts.  A brief demonstration of Novas’ verification enhancement solutions will follow.

Introducing SpringSoft – Who We Are, Our Products, and Our Vision

Presented by Scott Sandler, President of SpringSoft USA

Most design and verification engineers are familiar with Novas Software and Silicon Canvas solutions. But Novas and Silicon Canvas are just the tips of an iceberg.  SpringSoft is the foundation beneath the surface that has remained out of sight until now.  Get to know Springsoft:  who we are, our background, our products, and our vision for the future.