Collected Articles
2008
April 2nd, 2008
Taiwanese company to buy Novas - SCDsource
February 15th, 2008
Hantera verifieringsdata for SoC - EiN Magazine
February 8th, 2008
Faster Simulation and Enhanced Visibility Lead to Faster Verification Closure - SoC Central
January 28th, 2008
Benefits and Challenges of SystemVerilog - CiE
2007
December 8th, 2007
Annahmen und Ausnahmen - Design&Elektronik
November 29th, 2007
Visibility enhancement eases system validation for multicore SoCs - EDA TEch Forum
November 5th, 2007
Brown Bag Lunch: Sanguinetti & Sandler - EDACafe
October 11th, 2007
Verification: It's the Method-OLOGY, stupid! - CEO Viewpoint
October 11th, 2007
SystemVerilog-assertions i SoC-miljo - EiN
July 19th, 2007
Increase Visibility Into FPGA-Based Prototypes - Electronic Design Magazine
July 9th, 2007
Size Matters!; CEO Viewpoint - iDesign/Chip Design Magazine
June 24th, 2007
Verifiera NoC-baserade system med FPGA-prototyper - EiN
May 29th, 2007
Ameliorez la visibilite des signaux pour mieux deboguer le silicium - Electronque Magazine
May 14th, 2007
May 1st, 2007
Increasing Signal Visibility in FPGA-based Prototypes - Open Systems - NXT Book
April 24th, 2007
Novas Verdi Usage Doubles According to DeepChip Verification Tools Usage Survey Results
April 9th, 2007
Design-for-Debug Offers Inside Look at Signal Data - EE Times
April 2nd, 2007
Practical Applications of Data Abstraction Techniques for Embedded Systems Debug - SoC Central
March 29th, 2007
Increasing Signal Visibility in FPGA-based Prototypes - DSP-FPGA.com
March 19th, 2007
Got Visibility? - Chip Design Magazine
March 19th, 2007
Design Automation: Gate-level Timing Sim Revs Up - EE Times
March 15th, 2007
Solving Your Visibility Issues - Components in Electronics
March 15th, 2007
Erweiterte - Design & Elektronik
March 5th, 2007
Faster Verification is the Goal at ST - EE Times
February 28th, 2007
EDA Vendors Unveil SoC Design Trimmers - EE Times
February 28th, 2007
EDA vendors unveil SoC design trimmers - EE Times
February 5th, 2007
Post-Silicon Debug Worth a Second Look - EE Times
February 2nd, 2007
SystemVerilog Assertions in an SOC Environment - SoC Central
February 1st, 2007
Embedded Systems Debug - CiE Magazine
February 1st, 2007
Siloti Selected as Finalist in EDN Innovation Awards: Vote Today - EDN Magazine
January 15th, 2007
Maximizing Signal Visibility; Simulation Methods Needed to Reduce Verification Time - EE Times
2006
December 22nd, 2006
Siloti Wins Honorable Mention in Best in Test Awards - Test & Measurement World Magazine
December 15th, 2006
Siloti Makes EDN's Top 100 Products List 2006 - EDN Magazine
December 4th, 2006
Data Overload: Hardware Debug on Today's Embedded Platforms - ESS Magazine
December 1st, 2006
October 1st, 2006
October 1st, 2006
Fehlersuche bei FPGA-basierten Hardwareprototypen - E&E Magazine
September 20th, 2006
Visibility Enhancement Technology for Late-Stage Verification - SoC Central
September 14th, 2006
Konstruera och verifiera med SystemVerilog - EiN Magazine
September 12th, 2006
September 1st, 2006
September 1st, 2006
Hardware-Debugging: Das Fehler-Suchspiel - Elektronik Magazine
September 1st, 2006
Visibility Enhancement for Full-Chip Simulation - EDA Tech Forum
August 28th, 2006
August 25th, 2006
Harmonische Verbindung: Nexxim und Verdi - Elektronik Magazine
August 1st, 2006
Startups Collaborate on Simulation, Debug - EE Times
July 24th, 2006
EE Times User's Study Shows Novas #1 in Customer Satisfaction 5 Years in a Row - EE Times
July 17th, 2006
July 3rd, 2006
Transaction-level Debug in SystemVerilog Environment: the Best of Both Worlds - SoC Central
June 19th, 2006
June 12th, 2006
Solution de debogage d'un circuit de Novas - Electronique Magazine
June 1st, 2006
Novas CEO, Scott Sandler, Elected to EDAC Board - EE Times
May 2nd, 2006
CHIPit unterstützt Novas - Elektronik Magazine
May 2nd, 2006
Transparente Designs - Elektonik Magazine
April 27th, 2006
There's a Hole in the Verification Bucket Where Time and Energy Are Escaping - Chip Design Magazine
March 29th, 2006
First Debussy, then Verdi, now Siloti! - SoC Central (Clive Maxfield)
March 20th, 2006
Hardware/Software Modelling and Debug for ARM-Based Designs - CIE Magazine
March 20th, 2006
Visibility Enhancements – Novas - EDACafe
March 20th, 2006
Transaction models offer new deal forEDA
March 20th, 2006
Transaction Models Offer New Deal for EDA - EE Times
March 16th, 2006
In IC Design, You Can't Debug What You Can't See - Electronic Design
March 14th, 2006
March 13th, 2006
Siloti Visibility Enhancement (Taiwan)
March 10th, 2006
Novas Introduces On-the-Fly Debugging - EDN
March 10th, 2006
Siloti from Novas: what a great idea!
March 8th, 2006
DATE: Complex SoC Visibility Cuts Debug, Verification Time - Electronics Weekly
March 7th, 2006
Increasing Visibility in FPGA Prototypes and Emulators
March 7th, 2006
Tool Expands Design Debugging Functionality - Electronicstalk
March 7th, 2006
Increasing Visibility in FPGA Prototypes and Emulators - EE Times Programmable Logic DesignLine
March 6th, 2006
Novas Tool Lets Designer See Data from Debugging - EE Times
March 6th, 2006
Novas Gives an Idea of Chip Designs - Mrkt & Technik
March 6th, 2006
Novas Debuts Visibility Enhancement Tools - Test & Measurement World
March 6th, 2006
Altera, Novas Team for FPGA Visibility Enhancement - Electronic News
March 6th, 2006
Novas Tool Lets Designer See Data from Debugging - Embedded.com
March 6th, 2006
Novas Tool Lets Designer See Data from Debugging - CommsDesign
March 6th, 2006
Novas Adds Alexander Siloti to Its Orchestra - Gabe on EDA
March 6th, 2006
Neue Novas-Tools erleichtern Chip-Debugging - EE Times.de
March 6th, 2006
Novas Software accroît la visibilité de ses outils de débogage - Electronique
March 1st, 2006
Debug of Embedded SoCs Within a Distributed Team Environment - Embedded Systems Europe
February 1st, 2006
Picture This: HW/SW Co-Design - Electronic Products Design Magazine
January 31st, 2006
Full-Chip and Post-Silicon Verification: Visibility Issues
2005
December 1st, 2005
Goodbye Wires, Hello Objects - Electronic Systems & Software
November 1st, 2005
Is there a Practical Approach to Reducing Silicon Debug Time? - Chip Design Magazine
November 1st, 2005
Bugs in Design Are as Certain as Taxes - Chip Design Magazine
September 27th, 2005
Synfora Creating Tighter Integration to Novas tools - EE Times
September 26th, 2005
Hardware/Software Modeling and Debug of Embedded ARM Processor-based Designs - I.Q. Magazine
September 23rd, 2005
The High Cost of Verification - Electronic News
June 23rd, 2005
SoC Designers: Learn the What, Why, and How of Transactions - Electronic Design
June 16th, 2005
Consortium Focuses on IC Debug - Electronics Weekly
June 15th, 2005
Consortium to Address Silicon Debug - Test and Measurement World
June 14th, 2005
Consortium Formed to Address Design-for-Debug - EE Times
June 14th, 2005
EDA, Test, Debug Vendors Tackle Silicon Debug
June 13th, 2005
Novas Tops List for Customer Satisfaction - EE Times
June 2nd, 2005
EVE, Novas Integrate Verification Hardware and Debug System - EE Times
May 26th, 2005
SoC Hardware Debug Techniques Extended to System-Level - EDN Europe
May 10th, 2005
SystemVerilog se prête aux défis des nouvelles conceptions - Electronique Magazine
May 10th, 2005
SystemVerilog se prête aux défis des nouvelles conceptions - Electronique
May 10th, 2005
Bridging the Divide - New Electronics Magazine
April 19th, 2005
Erweiterte Debug-Umgebung - D&V 24.net
April 14th, 2005
Vers un outil de débogage matériel-logiciel des systèmes sur une puce - Electronique International
April 14th, 2005
SoC Hardware Debug Techniques Extended to System-Level - EDN Europe
April 1st, 2005
Coming Soon to a Debugger Near You: ESL Embedded Design Analysis - Embedded Systems Europe
March 21st, 2005
Design Comprehension and IP Communication - Components in Electronics
March 16th, 2005
Breathing Life Into Hardware and Software Codesign - Embedded Systems Programming
March 14th, 2005
Doing ESL Design: the Earlier, the Better - EE Times
March 3rd, 2005
GlobalPress Summit panelists debate route to working SoCs - EETimes UK
March 3rd, 2005
Debug Platform Targets SoCs Based On Embedded CPUs - Electronic Design
March 2nd, 2005
Novas Debugs Multi-processor - Electronics Weekly
February 28th, 2005
Novas Adds System Level Language Support to Debug Tool Portfolio - EDN
February 28th, 2005
System-level Verification Tackles SoCs - EE Times
February 28th, 2005
Debuggaus siirtyy järjestelmätasolle - Prosessori
February 22nd, 2005
Verifiera SoC Med Assertions - Elektronik i Norden
February 21st, 2005
Need for Debug Doesn't Stop at First Silicon - EE Design
February 1st, 2005
Communication Transactions Come First - SoC Central
January 28th, 2005
CEO Viewpoint: Understanding Design - Electronics Weekly
2004
December 4th, 2004
Transaction-based debug of PCI Express embedded SoC platforms - Compact PCI Magazine
December 3rd, 2004
Transaction-based Debug of PCI Express Embedded SoC Platforms - Compact PCI
December 1st, 2004
November 18th, 2004
Selecting Debug Tools for Embedded-Processor-Based systems - Electronic Products
November 15th, 2004
Behavioral Synthesis Tied to Verification - EE Times
November 1st, 2004
Debugging Approach for IP-laden Design - Chip Design Magazine
October 8th, 2004
Verification – Pulling It All Together - Electronics Weekly
October 4th, 2004
Integration Drives Embedded Software Development and Hardware Debug - EE Times
August 16th, 2004
Novas Linter Finds SystemVerilog Errors
June 4th, 2004
Novas Tops List in EDA Users Study for Customer Satisfaction
February 11th, 2004
Novas Tools Get Testbench Debug Boost
2003
December 11th, 2003
Verdi Selected by EDN As One of the Hot 100 Products Two Years in a Row
December 8th, 2003
Software Yields Graphical 'Views' From HDL Code - EE Times
November 3rd, 2003
Three Allies Take On 90-nm Verification
October 30th, 2003
August 11th, 2003
Novas offers mixed HDL debugging
July 21st, 2003
June 9th, 2003
Novas Software Ranked #1 in Customer Satisfaction (EE Times)
May 27th, 2003
Verification Technology Expands (EE Times)
May 26th, 2003
May 16th, 2003
Behavior-based debug is crucial for verification (EE Design)
April 3rd, 2003
Commentary: New Technology Targets Knowledge Reuse (e-insite)
March 31st, 2003
February 26th, 2003
Novas adds assertion support to debugger (EETimes)
2002
December 31st, 2002
EDA vendors brace for 90-nm challenge in 2003 (eedesign)
December 12th, 2002
Verdi Behavior-Based Debug System makes EDN's list of top 100 products of 2002
December 2nd, 2002
Novas systems to support Verisity verification language
November 1st, 2002
Expanding debug technology (Electronic Engineering Design - U.K.)
September 26th, 2002
Formalizing the debugging process (EDN)
August 1st, 2002
Design, Verification: What's the Difference? (EDA Vision)
June 24th, 2002
Debug and Design Exploration Tool Finds Out What Makes SoCs Tick (Electronic Design)
June 10th, 2002
EDA Behavior Patterns (Electronic News)
June 10th, 2002
Finding the DAC Theme (EE Times)
June 10th, 2002
From CAD to CAE to EDA, Design Tools Have Wrestled with Complexity (Electronic Design)
June 3rd, 2002
June 1st, 2002
Emerging Technology Awaits Engineers at 39th Annual DAC Convention (ECN)
May 31st, 2002
Good behavior for debugging (EEdesign)
May 13th, 2002
Novas, Verplex, and Verisity tweak verification solutions (EEdesign)
March 25th, 2002
Novas readies behavior-based debugging technology (EEdesign)
2001
December 10th, 2001
Novas Adds ECO Capability to Debussy Debugger (EETimes)
November 12th, 2001
EDA leaders trade places (EETimes)
October 12th, 2001
October 3rd, 2001
Consider the Human Element of Design (ISD)