Visibility Enhancement
First Debussy, then Verdi, now Siloti! - (SoC Central -- Clive Maxfield)
Full-Chip and Post-Silicon Verification: Visibility Issues
Is there a Practical Approach to Reducing Silicon Debug Time? - (Chip Design Magazine)
Consortium Focuses on IC Debug - (Electronics Weekly)
Consortium to Address Silicon Debug - (Test and Measurement World)
Consortium Formed to Address Design-for-Debug - (EE Times)
EDA, Test, Debug Vendors Tackle Silicon Debug
Need for Debug Doesn't Stop at First Silicon - (EE Design)
Novas Software accroit la visibilite de ses outils de debogage - (Eletronique)
Neue Novas-Tools erleichtern Chip-Debugging - (EE Times.de)
Novas Adds Alexander Siloti to Its Orchestra - (Gabe on EDA)
Novas Tool Lets Designer See Data from Debugging - (CommsDesign)
Novas Tools Lets Designer See Data from Debugging - (Embedded.com)
Altera, Novas Team for FPGA Visibility Enhancement - (Electronic News)
Novas Debuts Visibility Enhancement Tools - Test & Measurement World)
Novas Gives an Idea of Chip Designs - (Mrkt & Technik)
Novas Tool Lets Designer See Data from Debugging - (EE Times)
Tool Expands Design Debugging Functionality - (Electronicstalk)
Increasing Visibility in FPGA Prototypes and Emulators - (EE Times Programmable Logic DesignLine)
DATE: Complex SoC Visibility Cuts Debug, Verification Time - (Electronics Weekly)
Novas Introduces On--the-Fly Debugging - (EDN)
In IC Design, You Can't Debug What You Can't See - (Electronic Design)
Visibility Enhancements - Novas - (EDACafe)
Silicon Debug - (Test & Measeurment Word)
Visibility Enhancements for Full-Chip Simulation - (EDA Tech Forum)
Visibility Enhancements Technologly fpr Late Stage Verification - (SoC Central)