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Automated RTL/Gate Behavior Debug

Transaction-level Debug in SystemVerilog Environment: the Best of Both Worlds - (SoC Central)

Goodbye Wires, Hello Objects - (ES & S)

Synfora Creating Tighter Integration to Novas tools - (EE Times)

EVE, Novas Integrate Verification Hardware and Debug System - (EE Times)

SystemVerilog se prête aux défis des nouvelles conceptions - (Electronique Magazine)

SystemVerilog se prête aux défis des nouvelles conceptions - (Electronique)

Debugging Approach for IP-laden Design - (Chip Design Magazine)

Novas Linter Finds SystemVerilog Errors

Three Allies Take On 90-nm Verification

Find and Fix Problems Early in the Design Cycle - Breaking Down the Silent-Productivity Barrier: What's Next for Debugging?

Novas offers mixed HDL debugging

SystemVerilog Support Leads Debuggers' Upgrades - Database upgrades, clock-tree and timing debug features, and support for assertion-driven debugging have all been added to Novas' debug systems

Verification Technology Expands (EE Times)

What's Hot at DAC - New Tools and methodologies to be unveiled span system-level design to post-layout analysis

Behavior-based debug is crucial for verification (EE Design)

Expanding debug technology (Electronic Engineering Design - U.K.)

Design, Verification: What's the Difference? (EDA Vision)

Debug and Design Exploration Tool Finds Out What Makes SoCs Tick (Electronic Design)

Tool helps you get the bugs out (EDN)

EDA Behavior Patterns (Electronic News)

From CAD to CAE to EDA, Design Tools Have Wrestled with Complexity (Electronic Design)

Transeda and Novas Software Team to Increase Debug Productivity for Property-Driven Verification (EDAToolsCafe)

Emerging Technology Awaits Engineers at 39th Annual DAC Convention (ECN)  

Good behavior for debugging (EEdesign)

Novas, Verplex, and Verisity tweak verification solutions (EEdesign)  

Novas readies behavior-based debugging technology (EEdesign)