Session Topics for the 2006
Novas User Conferences
Automating SystemVerilog Assertion Debug
Advanced Methods for Debug and Analysis
Assertion-based techniques continue to gain in popularity, pushed along by the availability of standard languages such as SystemVerilog Assertions (SVA) and the ever-increasing number of tools that support assertion-driven analysis and verification methodologies. These tools produce a wealth of information that is used to detect and isolate problems, monitor coverage information to help gauge the quality and completeness of tests, and constrain/drive automated verification environments. However, processing and understanding this data poses new challenges to the debug environment.
In this session, we review assertion fundamentals - what assertions are, how they are used, and their impact on methodology - with focus on SVA and its benefits and impact on the debug process. We discuss the requirements associated with understanding and analyzing the operation of complex assertions, and describe new engines and associated visualization capabilities that address these requirements. Example applications and demonstrations based on the Verdi Automated Debug System are provided.
Eliminating Verification Overhead and Enabling Silicon Debug
Visibility Enhancement for Applications with Limited Signal Data
The EDA industry has dedicated significant effort over the last decade to improving the raw performance of verification tools. Simulators run faster and emulators and FPGA-based prototyping systems utilize silicon-based approaches to speed the process. At the same time, many companies are attempting to enable more efficient verification and debug of the actual silicon device - implementing specialized Design-for-Debug (DFD) logic on-chip to provide access to internal signal data during in situ testing of silicon prototypes. All of these tools and techniques suffer from the same fundamental problem - visibility. Understanding design operation - whether it is the simulation of an HDL description or the operation of the actual silicon mounted on a verification board - requires signal visibility, and obtaining this visibility is expensive. Simulation slows to a crawl and creates unmanageably large dump files. The "footprint" of the design on the emulator increases and its performance is sapped. In some cases, such as with FPGA-based prototyping systems and in situ testing, only limited signal data is available, and it usually corresponds to a netlist-level implementation of the design - making it even harder to interpret and understand from the designer's perspective.
In this session, we review the importance and impact of signal visibility on a wide range of verification applications, with focus on the inefficient methodologies dictated by this impact. We discuss a set of technologies that enhances visibility for these applications - enabling full visibility in the context of the RTL design when only a limited set of signal data is available - and propose more efficient methodologies based on these technologies. Example applications, demonstrations, and case study details based on the Siloti Visibility Enhancement products are provided.
Making Transaction-based Analysis Accessible to HDL Designers
Trends, Requirements, and Technology
The benefits of transaction-level design and analysis are well-documented. Transactions provide a means for models written at different levels of abstraction to communicate, allow verification and analysis tools to operate more efficiently on a higher-level stream of commands and data, and significantly ease the process of understanding and debugging design operation, abstracting away complex details and presenting functional information in a meaningful way. However, the lack of a broad transaction standard has generally limited their appeal and popularity to those doing system-level design - e.g., using SystemC, transaction-aware IP blocks, and specialized tools and environments tuned to a transaction-based process.
In this session, we review transaction fundamentals - what transactions are, how they are used, and their impact on methodology - with focus on the benefits related to the visualization, analysis, and debug of design operation. We also describe an SVA-based transaction description approach that makes the power and flexibility of transactions accessible to HDL-based designers. Example applications and demonstrations based on the Verdi Automated Debug System are provided.
Bridging the Gap Between Design and Implementation: Clock Analysis with Novas Tools
Requirements and Methods for Efficient Implementation and Optimization
Today's complex SOCs place increasingly difficult demands on clocks and clocking schemes. The competing requirements of high performance and low power consumption require complex clocking mechanisms that interact in dynamic and sometimes unexpected ways during design operation. This complexity presents a new source of potential design problems, and it usually takes several iterations between the logic designers and the physical implementation engineers to confirm the correct operation of and optimize the clock tree implementation details.
In this session, we review the typical clock tree implementation process, with focus on the cross-functional data and interaction requirements related to clock structure, design rule constraints, timing requirements, and clock tree synthesis strategy. We discuss efficient ways to obtain and share this critical information, describe a flow that enables front-end logic designers to prepare clock synthesis constraints in a systematic way, and show efficient mechanisms to verify the quality of clock tree synthesis (CTS) results - with the goal of significantly reducing the number of iterations required for correct and complete implementation. Example applications and demonstrations based on the Verdi Automated Debug System are provided.
Each session will be followed by a brief demo.
