Enhance Your Verification Methodology with Novas' Award-winning Debug Automation and Visibility Enhancement Technologies to:
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Cut your debug time in half
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Dramatically reduce simulation overhead
Explore Our Interactive Exhibits
Find out how many clock cycles it takes your design to produce as many value changes as there are stars in the galaxy. Find out how Novas can help you manage and make sense of this vast amount of data.
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"Size Matters"
See how you can reduce simulation file size requirements.
"What's Essential"
Learn how you can gain full visibility of your design with only a sample of signals.
Play on-line NOW and you'll be entered into a drawing for a Nintendo Wii.
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We'll also have in-depth demos on hand to show you specific solutions to meeting your verification challenges. You can demos on
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Reducing simulation overhead with our Siloti Visibility Enhancement System
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Debugging SystemVerilog with our Verdi Debug Automation System
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Silicon validation and debug with DAFCA and Novas
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Enjoying SystemVerilog
Presented by noted SystemVerilog expert Cliff Cummings
SystemVerilog continues to gain traction as the language of choice for next-generation design and verification. The combination of new data types and powerful RTL design constructs that make it possible to design more efficiently, support for assertions that enable adoption of a wide variety of assertion-based verification strategies, and an integral hardware verification language that enables constrained random test generation with functional coverage support - all rolled into a single, standard language - fulfills a vision discussed and espoused by EDA users and vendors alike for several years. However, to get the full benefit of SystemVerilog, engineers need to see the forest for the trees - which aspects of the language are important, which will help them accomplish their design and verification goals, and the challenges SystemVerilog introduces that require new ways of thinking and perhaps new tools and capabilities to augment their existing design and verification flows. This one-hour seminar - hosted by renowned SystemVerilog expert and industry consultant Cliff Cummings - will explore these questions and provide a framework for users to better understand SystemVerilog as they consider its adoption for current and future development efforts.
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Not only do we do more to solve your verification challenges, we're doing more for the community. For every person that stops by our booth, we'll donate a $1 to fund the Exploratorium Children's Education Outreach Program…A program dedicated to teaching underprivileged kids about science.
To learn more about the Exploratorium Children's Education Outreach Program go to www.exploratorium.edu/educate/outreach.html.