Exar Overcomes Mixed-Signal Design Challenges with Novas' Debug System
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Background
Exar Corporation (NASDAQ: EXAR) designs, develops and markets
high-performance, analog and mixed-signal silicon solutions for
the worldwide communications infrastructure. Leveraging its industry-proven analog design expertise,
system-level knowledge and standard CMOS process
technologies, Exar provides OEMs innovative, highly integrated
ICs that facilitate the transport and aggregation of signals in
access, metro and wide area networks. Exar's physical layer
silicon solutions address transmission standards such as T/E
carrier, ATM and SONET. The Company also
provides one of the industry's most comprehensive families of
serial communications solutions. Within this product
offering,
the low voltage and multi-channel universal asynchronous
receiver transmitters are particularly well suited to support
high data rate and increasing data transfer efficiency
requirements for various industrial, telecom and computer
server applications. In addition, Exar designs, develops and markets IC products that address
select applications for the video and imaging markets. It has
extended its traditional expertise in analog chip design to
create and deliver mixed-signal offerings with more than 30
years of experience and innovation in the digital and mixed
signal arenas. Exar's impressive customer
list includes Alcatel, Cisco, Hewlett-Packard, Lucent,
and Tellabs. The Company is based in Fremont, CA, had
fiscal 2003 revenues of $67 million, and employs approximately
265 people worldwide.
Mixed-signal design challenges
Mixed-signal chips offer complexity challenges, especially during the chip-level integration stage of the design process. During this phase, many different design elements come together and the verification process is complicated by not just the sheer size of the design (sometimes approaching five million gates), but also because many portions of the design are new to the engineer responsible for verification and debug. Exar uses a COT (customer-owned tooling) design flow where quick location of mismatches between RTL and gate-level design representations is critical to overall design success.
Factors such as these led Exar to look for a better way to address the verification and debug requirements of its newer and larger chip designs. A Senior Exar Design Engineer responsible for designing ASICs for SONET, T3/E3 and T1/E1/J1 applications, had used Novas' Debussy® Debug System in previous engagements, and he introduced Debussy to Exar as a way to navigate through unfamiliar designs and quickly track down error sources. For a family of data aggregation devices, which is capable of aggregating 12 DS3/E3/STS-1 into OC-12/STM-4, Debussy was an ideal solution.
The design team uses a Verilog-based design and spends up to 70 percent of the design process verifying its complex designs. Exar has used the waveform packages that come with simulation tools at the individual block-level, and for the most part they are sufficient because you're mainly working on your own code. However at the chip-level, it is much more complex where 8 and 12-channel designs are very hard to debug. When it comes to integrating it all together, the engineer has to be able to understand someone else's code, and standard waveform tools just don't provide that insight.
An Exar Vice President suggests, "Without the proper tools, there's only so much one engineer can do to interpret someone else's design, debug someone else's code, and trace connectivity issues back to their origins. With Novas' Debussy, we're able to verify items at the gate level, and navigate between source code views to get a complete picture of the connections between elements - which helps us reduce our debug time substantially."
A complete approach to debug
Unlike the bundled waveform packages Exar had been using, Debussy is a complete and independent system for locating, isolating, understanding and resolving design errors. Debussy provides visualization and analysis capabilities needed to help designers at both RTL and gate levels to build a mental map of design behavior, resulting in a quicker path to resolution. Based on an easy-to-use set of "point-and-click," and "drag-and-drop" techniques, Debussy gives designers an exact view of each design element, as well as a larger contextual view.
Using Debussy, Exar was able to locate, isolate and visualize relevant logic; trace objects in source code to find drivers and loads throughout the hierarchy; annotate verification results in the context of source code, and analyze the causes of value changes.
Debussy is built on an open, interoperable architecture that facilitates tight integration with popular verification environments and tools from leading EDA suppliers, so linking to Exar's existing simulation, synthesis, and timing tools was simple. As a result, Debussy extracts information from the design source code and connects that with verification knowledge captured from other tools. It uses this information to automate tracing of related elements to automatically analyze and locate the reasons for problems.
According to Exar's Engineering VP, "With Debussy, not only did we gain insight into the front end and the back end, but we were able to identify and understand much more quickly the relationships between the various aspects of the development cycle."
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