Speed Begets Speed:
DRC Uses Verdi debug to accelerate development time of
high performance reconfigurable co-processor
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DRC Computer Corporation is an innovative start-up that develops co-processing technology. Its chips are used in conjunction with AMD microprocessors to accelerate customized applications in high-end computer systems. The configurable devices it designs are used for compute-intensive applications such as financial modeling, oil and gas exploration, scientific analysis and pharmaceutical engineering — programs that typically run on supercomputers from companies like Cray and IBM. In short, they help make very complex software on very fast computers run even faster.
The company has pioneered what it calls the reconfigurable processing unit or RPU. Unlike a traditional central processing unit (CPU), the RPU is an FPGA-based device that can be configured for specific applications to offer fine-grained parallel execution of a particular algorithm. While a CPU is fixed hardware and executes software sequentially in a predetermined architecture, RPUs can be configured to run applications that are parallelizable, resulting in increased speed and efficiency. They work in concert with the main CPU while offloading certain tasks to accelerate run times, often from months to days.
The DRC RPU accelerator for the AMD Opteron CPU plugs into both 2-way or 4-way motherboards. Developers can port algorithm code over to the DRC RPU for acceleration, which works in tandem with the CPU. When acceleration is completed, results are sent back to the CPU via a standard interface such as HyperTransport™.
DRC chip designs are at the leading edge of complexity and performance, as highlighted with the introduction of its RPU 110-L200 
product. The company attributes the overall increase in capabilities of FPGAs (in their case, the Virtex™-4 family from Xilinx) as a key factor in the success of its strategy, enabling DRC to offer customers the ultimate in flexibility and field programmability.
Design challenges are a microcosm of the problems DRC solve
At the highest level, the challenges faced by the DRC development team when designing the RPU were essentially a microcosm of the challenges its own customers face when trying to solve complex problems — how do we make things go faster so we can accelerate our engineers. However, unlike the pure acceleration horsepower DRC applies to its customers’ applications, a part of the chip design solution it relies on is based on understanding design behavior to find 'hidden’ answers more quickly.
Like most advanced chip development teams, the engineers at DRC were faced with a design containing millions of gates and an intricate design structure. It was comprised of both internally developed logic as well third-party intellectual property (IP) blocks, along with multiple interface ports and memory controllers that all had to work together as a system. And, being in a competitive market space with short windows of opportunity, the clock was always ticking on each new design.
"Cost, time, and complexity are always key factors. You look for every advantage you can get,” said Babu Kandimalla, Design Lead for the RPU project.
A large portion of the development time for large complex designs such as the one behind DRC’s most recent product is spent in verification. Using a top-down, Verilog-based design flow, the DRC team spent close to three quarters of its overall schedule on verifying the correctness of the design. But not all of that is spent running simulations.
"Verification is really the challenging thing for us. We spend a lot of time trying to cut verification cycles to get to market quickly. But it’s not as easy as just applying more computer resources to the problem,” said Kandimalla.
When debug becomes complicated, Verdi helps simplify it
With a design of this complexity, debugging takes on an added dimension and scale. Tracking down errors in millions of lines of interconnected source code is both time consuming and tedious, keeping engineers from more valuable and creative work.
Fortunately, members of the DRC engineering team had previous experience with the debugging solutions from Novas Software, including its time-saving Verdi™ Automated Debug System. The Verdi system is a complete debug environment that combines traditional debug tools with a behavior-based approach that reduces the time required to find and correct errors by up to 50% or more over less automated manual methods. It uses a patented database of information and production-proven algorithms to find the root causes of behavior, regardless of the design’s origin. The system creates a comprehensive model of design behavior over time by combining the inferred logic with design simulation results. Information is presented in easy-to-use and familiar formats, such as waveform displays, source code browsers, or bubble diagrams.
Because of the amount of HDL code involved with their design, source code debugging is particularly an onerous task for the DRC team. The verification engineers at DRC run simulation in batch mode, get dump files, and spend most of their time viewing dumps. Because all of their verification tests are self-checking and run in regression mode, engineers know which tests are complete and can generate dumps for specific tests and debug at the source level.
Once they have the dump files, the Verdi system can read the design code. It provides an efficient way for DRC verification engineers to trace signal activity. Its powerful behavior analysis technology reduces manual tracing of activity across many clock cycles, enabling engineers to pinpoint the cause of errant behavior quickly. The team is able to view state machine names in symbolic fashion in both the source and waveform displays during source-level debugging with the system’s user-friendly active annotation capabilities.
Kandimalla explains the benefit, “We used to run the simulation, and then spend a lot of time looking at the waveforms. The waveform tools in Verdi are great, but the main way we use Verdi tools is for source-level debugging. You can easily trace loads and drivers to quickly find the driver responsible for syntax errors, for example.”
Debugging unfamiliar portions of the design also presents a challenge, but Verdi proved up to the task. “Even though we use off-the-shelf hardware, sometimes we need to get in there and tweak other people’s designs. It is important for us to understand the hierarchy of the third party IP, as well as how it interacts with the other elements of the design. Verdi really helps us to quickly get up to speed on the design even though much of the source code is unfamiliar,” Kandimalla said.
DCR also gets a big benefit from the state machine views the Verdi system offers. State machines are visualized in schematic fashion, providing a more intuitive view of the design. It also automatically generates state machines diagrams from RTL code, a feature which the DRC team uses extensively, especially for documentation purposes.
Verdi benefits extended to DRC customers
Because DRC processors are configurable, it is also important for them to extend the benefits of Verdi debug to their customers. Only 20% of the RPU design is occupied by DRC logic, leaving 80% available to end users for their applications. They can put their own user logic into the chip to interact with the DRC controllers.
Giang Le, Product Marketing Manager at DRC explains: “Our mutual objective is getting end products to market faster. We see how this tool will help us and our customers quickly determine whether a problem is in the user logic or the controller. We are definitely going to recommend that our partners and customers use Verdi to verify and debug their own complex logic.”
The bottom line: saving time
The engineering team has DRC estimated that an experienced designer using Verdi can reduce the time normally spent in debug by 1.5X. For a less experienced designer, perhaps as much as 2X. In either case, it equates to weeks, even months of time savings.
Not only does the Verdi system cut debug time, but it enables DRC engineers to develop and more rigorously verify complex designs with confidence. When debugging full-chip corner case bugs, the DRC verification team needs to browse through different hierarchies in the design and root cause the problem. The Verdi environment helps them to step through RTL from other engineers and locate the corner case bugs.
"Without question, Verdi helps us to speed up development time. Having this tool allows us to debug designs in a very effective way and improve productivity. I can’t do any debugging without Verdi,” Kandimalla concluded.