Picture Perfect Results with Verdi & Siloti
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One of the fastest-growing and fastest-changing consumer electronics markets is digital video and imaging. New products and applications for digital photography and video come to market at a breathtaking pace, which despite the sophisticated design challenges involved, make shorter development cycles a necessity for success. The challenge for any company involved in this market is to continuously enhance their products but at a faster pace than previous generations.
Ambarella is right in the middle of the digital video/imaging whirlwind. It develops the critical video compression and imaging processing chips that enable still cameras, video recorders and video-equipped devices such as cell phones to provide users with a high quality experience in a small form factor. The company states that its mission is to provide a solution that simultaneously delivers high-quality digital still and high definition digital video capabilities at a mainstream consumer price-point. This requires the latest video processing, image processing and video compression technology — all in an integrated low-power platform.
A new video CODEC chip introduced by Ambarella in September 2007, illustrates the time-and-complexity challenge they face. The Ambarella Ambacast™ 3000 processor more than doubles the computing power of its predecessors and can be programmed for increased video quality as well as encoding full 1080x1920 resolution HD at 60 frames per second in a single chip. The platform enables the design of broadcast encoders to increase picture quality, while the low power and high integration allows a reduced form factor and power consumption. As with most of their new products, the development team at Ambarella had a strict product schedule to hit in order for the Ambacast 3000 to stand a chance at success, and they were able to achieve their goals thanks in part to Novas debug and visibility enhancement products.
The Simulation Bottleneck
The design challenges involved with developing such a chip in the timeframe required meant Ambarella engineers needed every possible advantage they could find. Only the most efficient and intelligent design methodologies and tools will suffice when integrating and verifying 12 million gates of logic and memory, optimizing for 250MHz operating performance, and targeting a 65-nanometer manufacturing process.
Of particular concern in verifying video compression chips is simulation given the large streams of data associated with these designs. A single verification pass through all the regression tests can take up to an entire week because engineers have to run every frame of video into the simulator. That alone is challenging for time-constrained projects. But when a problem is found, the typical approach is to dump the entire waveform, which can take up to another two weeks. For Ambarella, which faces the challenge of significant increases in design size with each new generation of its chip, those types of run times are unacceptable.
“We have very rigid time constraints for each step of our design process and that includes simulation. We can’t simply extend beyond the schedule, so we must be as efficient as possible in terms of things like debug and waveform dumping,” Chan Lee, Vice President of VLSI at Ambarella. “We want to leave as much time as possible to thoroughly test the design, and wasting time tracking down bugs or waiting for a waveform to dump prevents us from doing that.”
The Ambarella team uses a Verilog-based design flow and has evolved to using SystemVerilog as well. Initially their SystemVerilog usage focused on the design efficiency advantages of the high-level language, i.e., writing complex structures using less code. In addition to the benefits of shorter simulation run time, fewer lines of code typically lead to fewer bugs. They have expanded their usage to also include testbench creation.
Rudi Rughoonundon, Senior Engineer at Ambarella explained further, “We really push the RTL as hard as possible to get the most out of it, but can’t afford to wait around for tools to run. This is one of the reasons that our design flow coupled nicely with Novas and its time-saving verification enhancement solutions.”
Verdi Automation Good Fit for Large, Complex Design
Support for SystemVerilog was a key factor in the Ambarella team’s decision to look at the Verdi™ Automated Debug System from Novas. They had also heard good things about the stability and capabilities of the Verdi product, which seemed well suited for their size and complexity challenges.
Much of their initial deployment of the Verdi system was focused on the RTL level debug process, and they were impressed with both the performance and efficiency of the tool. For example, the Verdi X-tracing feature enabled engineers to automatically trace back to the original source of an X without getting ‘stuck’ along the way. This was particularly helpful when dealing with third-party IP. The ability to debug memory elements also proved to be faster than what they had been using, saving valuable time in the overall verification schedule.
Ambarella engineers also found great value in the Verdi active annotation capability. “Active annotation is critical because it allows us to look at the source code and signal values at a given point in time. Before, we had to have multiple display windows, a piece of paper, and then manually calculate the values. With Verdi, it’s all automated and streamlined.”
“Verdi probably saved us 50 percent in overall debug time, which is extremely beneficial in terms of giving us time to run more tests. It’s what gets us the most bang for the buck, by increasing the confidence level that we are going to get clean silicon,” said Rughoonundon.
Siloti Essential to Reducing Verification Overhead
The quest for faster, better verification methods did not stop with Verdi debug. Ambarella engineers next turned to Siloti™ Visibility Enhancement from Novas. Essentially, the Siloti approach is to eliminate the overhead associated with dumping data for all the signals in a design. It provides engineers with full visibility of internal signals by identifying the minimal “essential” set of signals required for dumping, and then generates “on-demand” the rest of the signal data. Gate-level results are automatically correlated to the RTL source code, enabling debug at a more familiar level of abstraction.
Ambarella’s Lee commented, “Siloti was pretty amazing. We could dump out gate-level simulations at a very high speed. We used it for full-chip simulations, because it would have been impossible to dump out data for the entire project otherwise. I’m not sure what we would have done without Siloti,”
Indeed, the most significant challenges Ambarella faced from a development schedule standpoint were related to raw throughput of the verification tools. This was especially evident during simulation, which could often take weeks for a given set of tests depending on the amount of waveform data dumped and the number of iterations required to isolate any detected bugs. To help them overcome this obstacle, Ambarella engineers called upon Siloti and its essential signal analysis (ESA) capability.
Ambarella incorporated Siloti into their flow, scripting it to run Siloti ESA automatically prior to simulation to generate the minimal list of signals for dumping. Simulation run times were about 2x that of a no-dump run with dump files 4x smaller than those produced by a full signal dump.
“This resulted in a much more thorough and efficient verification process with no loss in visibility during debug, thanks to the Siloti capability for on-demand data expansion (DE) within the Verdi debug environment,” explained Rughoonundon. “We used Siloti at the RTL and gate level, and each time it saved us significant run time. Siloti should win a prize. It’s way ahead of its time.”
About Ambarella
Ambarella is the technology leader in low-power, high-definition video compression and image processing semiconductors. Ambarella products are helping to define a new class of hybrid digital cameras that bring consumers unmatched high definition video and digital still images together in one device. Many cameras and camcorders have been shipping using Ambarella A2 SOC. For more information on the Ambarella product line, please visit http://www.ambarella.com/.