ADC slashes design time with Novas debugging system
Company Overview
Development challenges
Many of its products rely on high performance ASICs, which involve a hand-off between ADC's internal development teams and their ASIC suppliers. This hand-off can cause schedule delays if multiple design iterations are required, particularly to locate and correct timing errors.
A key ASIC project
Ron Munoz heads a design group within ADC's development operations in Raleigh, North Carolina. Lam Chan, one of the designers in the group, was chartered with finishing an important ASIC for ADC's T1/E1 repeater products, which solve problems with signal deterioration and extend signal quality over long distances.
The design was actually one that Ron's group had adopted from another ADC design facility, presenting problems with design familiarity. "We didn't have a lot of understanding of the original designers' intent. It was like doing an ASIC blindly," Lam said.
Further compounding the challenge was the fact that the design had originally been done in VHDL, and the Raleigh group was Verilog-based. Their job was to ready the design for hand off to the ASIC vendor, with a particular focus on solving some critical timing problems they knew plagued the design. While not overwhelmingly large - roughly 100K gates - the design did present some difficult timing issues such as race conditions, setup and hold times, and clock issues.
Ultimately, the ASIC was to be used to prototype a new product on which the company was counting. "Obviously time to market is critical in a business like ours, so part of our job was to cut the back-end effort required to get the chip to work in manufacturing. We had to make sure it was functionally correct to ensure a clean passthrough," Lam explained.
A new
debug strategy
They decided to look at the Debussy® Knowledge-Based Debug System from Novas Software, which offers an integrated set of viewing and analysis tools for debugging complex ICs. Through Debussy's ability to allow designers to visualize, trace, annotate and analyze portions of designs quickly and easily, the ADC team hoped to shave valuable time off their design time and reduce the number of iterations with its ASIC vendor.
"The timing problems are not easy to solve, especially when you're dealing with an unfamiliar design. Waveform viewers that come with simulation tools make it very difficult to track down x's. Novas' system made it a lot easier," Lam said.
The ADC designers particularly liked the integration of the various capabilities within Debussy, including those for simultaneous and linked viewing of:
Schematics: Novas' debug-specific schematic visualization tool generates interactive logic diagrams showing the structure of selected portions of a design. It annotates diagrams with simulation results and cell/wire SDF delays for review in context. Its analysis includes location and isolation of bus drivers with conflicting values and calculation of delays along a path.
Netlists: A powerful tool within Debussy displays the design hierarchy and Verilog source code for selected design blocks. HDL elements are hyperlinked for easy automatic tracing of cause and effect.
Waveforms: A state-of-the-art graphical waveform display is fully integrated with the rest of the Debussy system. With it, ADC designers were able to click a waveform to find its drivers or loads, or click an edge to find the actual driver at that time.
This integration gave the Raleigh team the chance to cross-probe across different views and parts of the design, and quickly pinpoint causes of timing problems.
The Debussy system extracts and stores structural knowledge of a design and its simulation results and provides easy access to this information through its Design Knowledge Architecture. This foundation helped the ADC team quickly locate, isolate, understand, and resolve errors in their ASIC.
"It's really a much more powerful and efficient way to find errors," Lam explained. "We had particular problems with race conditions and clock issues, but we were able to track them down and fix them very quickly with the Novas system."
Debussy also worked seamlessly with their existing design environment, including their Verilog-based simulator. Debussy provides a highly intuitive way to trace and visualize design structure and correlate it with simulation. "We rely on tools mainly from a single EDA vendor, but there were no issues in integrating the Novas tools into our flow," Lam said.
Saving time: the ultimate benefit.
Lam says Debussy allowed him to do just that, cutting up to 8 weeks of design time from their schedule. As a result, the end product was rolled out 2 months earlier, a major business benefit to ADC.
"If you think about the number of units per month we can ship, plus the competitive advantage of being on time or early to market, the time we saved with the Novas' system is very important," Lam concluded.