Novas Customer Success Stories
Check out how some of our customers have used our debug system to cut debug time in half.
ADC Slashes Design Time with Novas Debugging System
Product:
Fiber optics and network equipment
Challenges:
-
Time-to-market and cost reduction
-
Large complex designs
-
Multiple design teams in disparate locations
Why Novas?:
-
Allows design team to visualize, trace, annotate, and analyze portions of designs quickly and easily
-
Provides integration of various capabilities within the debug system (schematics, netlists, waveforms)
-
Works seamlessly with existing design environment
"If you think about the number of units per month we can ship, plus the competitive advantage of being on time or early to market, the time we saved with the Novas system is very important."
Lam Chan, Designer, ADC
Picture Perfect Results with Verdi & Siloti
Product:
Video compression and imaging processing chips
Challenges:
-
Strict time-to-market schedule
-
Simulation of large streams of data
-
Waveform data dumping takes weeks
Why Verdi?:
-
Provides ability to understand someone else's work
-
Allows automated tracing of design behavior over multiple clock cycles that reduced debug time
-
Significant performance and efficiency at RTL level debug
-
Ability to debug memory elements faster, saving value time in their overall verification scheduled
"Verdi probably saved us 50 percent in overall debug time, which is extremely beneficial in terms of giving us time to run more tests. It’s what gets us the most bang for the buck, by increasing the confidence level that we are going to get clean silicon,” - Rudi Rughoonundon, Senior Engineer, Ambarella
Why Siloti?:
- Eliminates the overhead associated with dumping data for all the signals in their designs
- Provides full visibility of internal signals by identifying the minimal “essential” set if signal required for dumping
- Generates the minimal list of signals for dumping
“This resulted in a much more thorough and efficient verification process with no loss in visibility during debug, thanks to the Siloti capability for on-demand data expansion (DE) within the Verdi debug environment,” explained Rughoonundon. “We used Siloti at the RTL and gate level, and each time it saved us significant run time. Siloti should win a prize. It’s way ahead of its time.” - Rudi Rughoonundon, Senior Engineer, Ambarella
DRC Uses Verdi Debug to Accelerate Development Time of High Performance Reconfigurable Co-processor
Product:
RPU Accelerator for AMD Opteron CPU
Challenges:
-
Quickly understand complex design behavior to find 'hidden' answers
-
Cost savings
-
Cutting verification cycles to get to market quickly
Why Verdi?:
- Previous experience with Verdi
- Verdi provides traditional debug with behavior-based approach
- Cuts debug time by 50% or more
- Verdi provides an efficient way to trace signal activity
"Without question, Verdi helps us to speed up development time. Having this tool allows us to debug designs in a very effective way and improve productivity. I can't do any debugging without Verdi " - Babu Kandimalla - Design Lead for RPU project at DRC
Debugging to Reach Tapeout within 8 Short Months
Product:
Class-D intelligent digital ampliphiers
Challenges:
-
Aggressive 8 month product development schedule
-
Debugging a large amount of 3rd party IP
-
Cutting design time while allowing efficient enhancements in product functionality
Why Verdi?:
-
Provides ability to understand someone else's work
-
Allows automated tracing of design behavior over multiple clock cycles that reduced debug time
-
Integrates seamlessly into D2Audio's verification environment
"Verdi was pivotal in accomplishing our design goals. It was a tool that we had to have. It wasn't an option. We could have found all the errors given enough time. But, with Verdi, we came to resolution very quickly, which helped us stay on schedule."
Joel Page, IC Design Manager, D2Audio
Navigating Unfamiliar Territory
Product:
Next-generation semiconductor products for broadband communications
Challenges:
-
Integrating 3rd party soft synthesizable core resulted in the need for advanced debug
-
Needed to understand design behavior over time
-
Simple waveform viewers that come with simulators were difficult to debug with for large, complex design
Why Verdi?:
-
Provides an intuitive way to analyze cause/effect relationships, visualize design behavior, and explore alternate behaviors
-
Works well debugging imported design elements and code from other team members
-
Cuts debug time significantly to make design schedules more attainable
"I was lucky enough to see a demo of Verdi and was impressed with its features. Frankly, after having used it now for awhile, it's difficult to see how powerful it really is just from the demo."
John Coates, VLSI Designer, Entropic Communications
eSilicon Accelerates Design Cycles with Novas Verdi Debug System
Product:
Customer ICs
Challenges:
-
Navigating large, complex designs
-
Distributed engineering teams
-
Understanding 3rd part design elements
Why Verdi?:
-
Ability to quicky trace and analyze causes of complex problems
-
Easily integrates into existing methodology design flow
-
Help to quickly and easily comprehend unfamiliar designs
"Novas' Verdi system provides the ability to quickly trace and analyze the causes of complex DFT issues, saving valuable time and effort. The end result is higher quality for hand-off to manufacturing. Since we use tools from a variety of EDA suppliers, we also appreciate how easily the Novas debug platform integrates into our state-of-the-art design flows."
Joe Reynick, Director of DFT and EDA solutions, eSilicon Corp.
Debug Automation Drives Productivity
Product:
Complex audio/video devices
Challenges:
-
Strict time-to-market pressures
-
Reduce the amount of time spent on debugging
-
Needed to understand behavior of the design
Why Verdi?:
-
Seeing the entire pertinent behavior in one go saves signficant time
-
Views that present behavior in a simplified easy to understand fashion
-
Working with many tools and languages makes using the environment easy
"Debugging is like wandering through a maze, where you can only see where you are going one turn at a time. Verdi allows the maze wall height to be reduced so that you can see where you need to go, and this helps you get to the end point much faster."
Irwan Sie, Director of IC Design, ESS, Inc.
Exar Overcomes Mixed-Signal Design Challenges with Novas' Debug System
Product:
Mixed-signal chips
Challenges:
- Large, complex 5 million gate design
- Verification engineers unfamiliar with design
- Simulator provide waveform tools insufficient
Why Novas?:
- Provides a complete and independent system for locating, isolating, understanding, and resolving design errors
- Utilizes easy-to-use "point-and-click" and "drag-and-drop" techniques
- Is built on an open, interoperable architecture that facilitates tight integration with popular verification environments and tools from leading EDA suppliers
"With Debussy, not only did we gain insight into the front end and the back end, but we were able to identify and understand much more quickly the relationsips between the various aspects of the development cycle."
Vice President of Engineering, Exar
LSI Logic Relies on Debussy to Manage Unfamiliar Design Challenges
Product:
ASIC Design Services
Challenge:
-
Engineers tasked with working on customer designs originally developed by someone else
-
Understanding of the behavior of all the design elements
-
Simulator provided waveform tools cannot handle large complex designs
Why Novas?:
-
Helps engineers better undertand design behavior even for unfamiliar design through an efficient, integrated set of visualization tools
-
Cuts time spent in debug by half or more
-
Easy tool set up
"Say our design center does 15 ASICs a year. If we can get our debug time down from three days, which had been typical, to a few hours with Debussy, we can save a lot of money. Plus the time would have lost can be used doing more productive things, such as working more closely with the customers."
ASIC Design Team Member, LSI Logic
Network Elements Debugs Complex Optical Networking Design with Novas
Product:
LiMPM 10 GB/s Optical Networking Module
Challenges:
-
Need to traverse hierarchies in large, complex and datapath oriented designs
-
Need for design teams to quickly debug unfamiliar designs
Why Novas?:
-
Links betweek multiple design views
-
Provides highly intuitive method to trace and visualize design structure and correlate it with simulation results
-
Can be used at multiple levels of abstractions and points in the design process
"Our success is based largely on the rate at which we can identify a bug, fix it and move on with the design. Debussy allows us to do that very quickly."
Don Primrose, Director of Digital IC Development, Network Elements
Siloti Visibility Enhancement Products Ease P.A. Semi's System Validation Burden
Product:
PWRficient family of 64-bit multicore processors for the high-performance embedded, consumer and computing markets
Challenges:
-
Running emulation on large designs can take a long time to reach the point of failure
-
Debug can be error prone and take a significant amount of time and resources
-
Needed visibility into the design without a negative impact on performance
Why Novas?
-
Siloti Visibility Enhancement products address the costly problem of decreasing visibility into the functional operation of complex ICs during late-stage verification and system validation
-
Patent-pending visibility enhancement technology accelerates the process of understanding and repairing sources of erroneous behavior
-
Siloti VE data expansion and abstraction correlation engines optimize verification while minimizing the impact of observation.
"We used Siloti to test emulation and to debug failures directly in emulation, without a simulation dump. This allowed us to zoom in on problems quickly - within a day or so. By comparison, if we had run a lone application or operating system, it would have taken us anywhere from days to more than a week to run instructions in the simulation model and get enough significant information via a signal dump to perform debug."
Mike Dickman, principal engineer in charge of testing platforms, P.A. Semi
Verdi Debug System Key Element in P.A. Semi Verification Strategy
Product:
PWRficient family of 64-bit multicore processors for the high-performance embedded, consumer and computing markets
Challenges:
-
High complexity, multiple components, high level of integration
-
Fast, efficient debug
-
Maintaining short time-to-market
Why Novas?
-
Verdi has capabilities and benefits other solutions lacked
-
Ease of use
-
Interoperability with many design and verification tools
"Tracing an unknown physical problem through a complex design during silicon debug is a process that can take an entire day. With Verdi, we will be able to narrow down a silicon problem in less than an hour. This will dramatically shorten the team's debug time and result in an order of magnitude productivity improvement. It will also help ensure that the P.A. Semi maintains its tight time-to-market schedule."
Tse-Yu Yeh, director of architecture and verification, P.A. Semi
SigmaTel Relies on Verdi Debug System As Critical Element in Verification Strategy
Product:
Mixed-signal multimedia ICs for use in portable and consumer electronics products - STMP 3600 series SoC platform
Challenges:
-
Use of 3rd party IP increased design complexity
-
Need for design teams to quickly debug unfamiliar designs
Why Novas?:
-
Ease of use
-
Large buy-in from the design community
-
Great value in cutting design time with an efficient debug strategy
"Novas is very good at anticipating our needs and the tool is ahead of us in terms of its capabilities. It's reassuring to know that the Verdi tool is capable of supporting the growing needs of my design team."
Bryan Cope, Systems and Digital IC Design Engineer, SigmaTel
Verdi System Deployed by TAEC Design and Verification Teams to Accelerate Debug of Custom SoC and ASIC Solutions
Product:
Custom system-on-chip and ASIC designs
Challenges:
-
Design complexity
-
Significant use of third-pary IP
-
Time and cost constraints on engineering efforts
Why Novas?
-
Able to quickly and easily trace unknowns
-
Multiple viewing and analysis perspectives allows easier understanding of the design
-
Automated debug methodology
"Our teams work on extremely complex designs with advanced process technologies, often involving very large gate counts and significant amounts of third-party IP. These factors increase the magnitude of the verification challenge and impose additional time and cost contraints on our engineering efforts. With the Verdi system, we are able to implement a much more effective, automated debug methodology for finding problems faster and earlier in the development cycle."
Shigenori Imazato, Vice President of Engineering, TAEC SoC Design Centers
Unisys Tackles 6 Million-Gate Design with Novas
Product:
ES7000 family of high-end servers
Challenges:
-
Needed powerful verification capabilites to handle extremely large design size and complexity
-
Meeting time-to-market schedule
-
Needed higher level integration
Why Novas?:
-
Provides a unified view of the waveform and source code and ability to move between them
-
Allows designers unfamiliar with the design to become very productive quickly
-
Can be used with any simulation tools
"Meeting our schedule is always the most important thing, and with Debussy our productivity improvement was significant. Debussy made it possible to meet the challenges we faced with regard to higher levels of integration and design size on an ASIC that is critical to future generations of enterprise servers from Unisys."
Craig Church, Design Team Manager, Unisys