Events

See Our Demos at DAC - Booth 1300

We’ll show you how to cut debug time in half and eliminate simulation overhead

Siloti™ Visibility Automation System Demo

Siloti transforms simulation methodologies by eliminating the overhead of recording signal data. The results are much faster simulations with full visibility into design operation, enabling more efficient full-chip verification methodologies and the elimination of the severe data management problems associated with capturing and storing huge simulation results files.

With Siloti, instead of suffering huge run times and massive signal dump files or iterating over multiple simulation runs until you capture the right signals to understand design behavior, you can record a minimal subset of signals without any loss in visibility during analysis and debug. Siloti identifies the signals essential for full visibility and then expands the rest of the data on-the-fly from this minimal subset – all with little or no setup by the user. Simulation times are typically only 40% longer than simulations with no signal recording, and file sizes are reduced by 75% or more compared with full signal recording. As costly iterations are eliminated, the time required for each verification+debug cycle becomes predictable, and your schedule stays on track.

What we’ll be showing

Essential Signal Analysis (ESA) to identify the critical subset of signals that must be recorded during simulation
On-the-fly Data Expansion (DE) to enable full visibility during debug (Verdi)
Replay for timing-accurate regeneration of signal data based on the Essential Signal (ES) data set

What’s new for 2008

Enhanced ease-of-use: Get the benefits of Siloti with little or no impact on existing Verdi debug flow
Replay: Get the benefits of Siloti – faster simulations and smaller FSDB files – with gate-level timing simulations

Verdi™ Automated Debug System Demo

Verdi’s unique Behavior Analysis (BA) technology automates the debug process and significantly reduces the time required to understand design behavior and isolate the causes of incorrect operation. Using Verdi, you can reduce debug time by more than 50% compared to other debug solutions, giving you back precious time that you can apply to more important tasks.

Verdi has quickly become the de-facto standard for understanding, analyzing, and debugging SystemVerilog code. You can trace activity through SystemVerilog designs using powerful behavior analysis technology, automate the debug of SystemVerilog Assertions (SVA) and check them off-line using Verdi’s Assertion Evaluator, and log critical information from your SystemVerilog Testbench (SVTB) code to debug and trace activity from the design back to the testbench. You can also review and analyze your SVTB code in unique ways tailored for the software-like nature of these descriptions.