Novas User Conference Topics:
Getting the Most Out of SystemVerilog (U.S. conferences only)
Hosted and presented by Cliff Cummings
SystemVerilog continues to gain traction as the language of choice for next-generation design and verification. The combination of new data types and powerful RTL design constructs that make it possible to design more efficiently, support for assertions that enable adoption of a wide variety of assertion-based verification strategies, and an integral hardware verification language that enables constrained random test generation with functional coverage support - all rolled into a single, standard language - fulfills a vision discussed and espoused by EDA users and vendors alike for several years. However, to get the full benefit of SystemVerilog, engineers need to see the forest for the trees - which aspects of the language are important, which will help them accomplish their design and verification goals, and the challenges SystemVerilog introduces that require new ways of thinking and perhaps new tools and capabilities to augment their existing design and verification flows. This one-hour seminar - hosted by renowned SystemVerilog expert and industry consultant Cliff Cummings - will explore these questions and provide a framework for users to better understand SystemVerilog as they consider its adoption for current and future development efforts.
Applications for Siloti Visibility Enhancement
Technology
The Siloti™ Visibility Enhancement solution from Novas Software makes verification more efficient by significantly reducing the overhead of capturing signal data while still providing full visibility of the signals in the design. Recording all signal values creates huge unmanageable data files while dumping no data or partial data can result in an unpredictable number of simulation iterations. Siloti analyzes the RTL or gate-level design to define a minimal and sufficient set of signals to be dumped. Siloti then expands the limited "essential" signals on demand to provide full visibility as needed. With less signals to be dumped, Siloti enables the simulator to run with minimal overhead and creates much smaller and more manageable file sizes. This presentation will provide an introduction to Siloti and analyze real world applications for full-chip simulation and emulation methodologies.
Performance and Capacity Enhancements to the
Verdi Automated Debug System
As a leading advanced debug solution, the Verdi™ Debug Automation System has evolved to keep pace with today's large digital designs and the latest technology trends for verification methodologies. The increases in complexity and newly adopted methodologies such as SystemVerilog Assertions and SystemVerilog Testbench require more efficient debugging capabilities than those of traditional HDL debug. The latest advancements to the Verdi debug system delivers 3 to 10 times more performance and capacity and will help you understand and accelerate your verification process when using SystemVerilog Assertions and SystemVerilog Testbench methodologies. This presentation will showcase the latest capabilities and demonstrate how you can take advantage of them in your next design.
Hints and Tips for Using Novas Solutions More Effectively
Verification and debug can be an incredibly time consuming and costly process without the right tools and the knowledge to use them. In this tutorial, we'll show you how get the most out of your Novas systems to enhance your verification methodology. We'll provide you with practical ideas on how to approach specific verification scenarios using our Verdi Debug Automation and Siloti Visibility Enhancement solutions. You'll also learn how to take advantage of new features and those you have but may never have used. You'll walk away with valuable hints and tips on how you can cut your debug time even further and reduce verification overhead.